Calibration techniques in nyquist AD converters

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Table of contents
; P: B4 N* @$ q: XList of abbreviations
List of symbols
Preface
4 M- K) g$ z4 W8 A& K- b1 Introduction 1
1.1 A/Dconversion systems . . . . . . . . . . . . . . . . . . . . . . 1
" s( r5 p# l: y! p0 x1.2 Motivation and objectives . . . . . . . . . . . . . . . . . . . . . . 5
  W$ C" `, z! E9 Z1 A7 {/ f1.3 Layout of the book . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Accuracy, speed and power relation 7
" |: t9 l" S: D4 Z! E6 |  \2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
" p1 R2 A% |6 g, J6 ?+ @; {" @  l2.2 IC-technology accuracy limitations . . . . . . . . . . . . . . . . . 8
2 w) V' I9 b8 D. }. l) |2.2.1 Process mismatch . . . . . . . . . . . . . . . . . . . . . . 8
$ |6 _  J& _- N6 @* Z* Y2.2.2
2.2.3 Matching versus noise requirements . . . . . . . . . . . . 11
2.3 Speed and power . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Maximumspeed . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
0 x2 @3 ~2 R5 C$ b- y4 k2.5 . . . . . . . . . . . . . . . . . . . . . 15
2.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
9 l7 c' F4 n7 w  N  y6 f3 A/D converter architecture comparison 21
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8 z2 K7 T1 f. H1 p  I3.2 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.2.1 Fullflash . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.2 Interpolation . . . . . . . . . . . . . . . . . . . . . . . . 26
3.2.3 Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3 Folding and interpolation . . . . . . . . . . . . . . . . . . . . . . 33
3.4 Two-step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1 o& X+ q5 q* t* tThermal noise . . . . . . . . . . . . . . . . . . . . . . . 10
CMOS technology trends
, p1 O" u+ v2 b: U. B9 jxi
xiii
' Q9 @- i. v$ F+ w; yxvii
9 n/ L% o3 t6 M/ ]7 U. J& ~2 gTable of contents
3.5 Pipe-line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.6 Successive approximation . . . . . . . . . . . . . . . . . . . . . . 54
3.7 Theoretical power consumption comparison . . . . . . . . . . . . 56
: F( Y% C' E. ^2 T9 t3.7.1 Figure-of-Merit (FoM) . . . . . . . . . . . . . . . . . . . 57
: ?$ {. u) q# y$ }# e3.7.2 Architecture comparison as a function of the resolution . . 57
3.7.3 Architecture comparison as a function of the sampling speed 65
3.8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
, H! F/ j1 v6 j# N3 E1 v1 j( Y4 T4 Enhancement techniques for two-step A/D converters 67
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.2 Error sources ina two-step architecture . . . . . . . . . . . . . . 67
4.3 Residue gain in two-stepA/Dconverters . . . . . . . . . . . . . . 69
/ @! e1 |9 Z2 i. l' ?2 I: p4.3.1 Single-residue signal processing . . . . . . . . . . . . . . 69
4.3.2 Dual-residue signal processing . . . . . . . . . . . . . . . 71
4.3.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.4 Offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 75
+ z7 Z8 w! O- S9 g6 q& L2 B9 X4.4.2 Calibration overview . . . . . . . . . . . . . . . . . . . . 75
0 A# B9 H7 D" m: j+ P5 h! {7 m5 M4.4.3 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.5 Mixed-signal chopping and calibration . . . . . . . . . . . . . . . 83
/ C( Q  T9 t& l, T5 S4.5.1 Residue amplifier offset chopping . . . . . . . . . . . . . 83
: }6 d+ @, h: U, o4.5.2 Offset extraction fromdigital output . . . . . . . . . . . . 84
4.5.3 Pseudo random chopping . . . . . . . . . . . . . . . . . . 88
$ h; Q. [& c& s' Q9 A4.5.4 Offset extraction and analog compensation . . . . . . . . 91
& @; F+ C/ u1 I4 _! v1 C- h4.5.5 Offset extraction in a dual-residue two-step converter . . . 93
4.5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . 102
5 A 10-bit two-step ADC with analog online calibration 103
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
8 z. \. |# m! }5 k6 q$ @: ]5.2
5.2.1 Coarse quantizer accuracy . . . . . . . . . . . . . . . . . 106
5.2.2 D/A converter and subtractor accuracy . . . . . . . . . . . 107
5.2.3 Coarse andfineA/Dconverter references . . . . . . . . . 108
5.2.4 Amplifier gain and offset accuracy . . . . . . . . . . . . . 109
5.3 Circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.3.1 Track-and-hold circuit . . . . . . . . . . . . . . . . . . . 111
; a2 C: |4 y1 h. J8 c9 G3 E& Z5.3.2 CoarseA/D,D/Aconverter and subtractor . . . . . . . . . 111
  Y. l  v, A3 N' }8 S7 |5.3.3 Coarse ladder requirements . . . . . . . . . . . . . . . . . 112
5.3.4 Offset compensated residue amplifier . . . . . . . . . . . 113
4 t! E9 s& D+ R9 R( k5.3.5 FineA/Dconverter . . . . . . . . . . . . . . . . . . . . . 114
5.3.6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
: p9 }# f3 P0 dviii
( N6 X# `+ j# oTwo-Steparchitecture . . . . . . . . . . . . . . . . . . . . . . . 105
- s' M2 e0 A5 z+ R+ ZTable of contents
5.4 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . 117
5.5 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
" L  G: X$ r9 ?8 C& U5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6 A 12-bit two-step ADC with mixed-signal chopping and calibration 123
7 A low-power 16-bit three-step ADC for imaging applications 149

xp212125o

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tuza2000

good material !!!