hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs

* ^  V+ z; Y7 v要怎麼定義用
5 L' R5 w5 J5 L( f' @$ |1 Pplot LX??
6 ?! M2 `" i: ~1 ?& ?9 y
請各位幫忙一下

小朱仔

直接下.op及.probe
  K! d: D: F/ k8 q7 U- w% m找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .

Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.
) A0 ]6 h& y& K( X1 M, v; C
# _" ^" @1 Z6 P. U* n
! \( `: T: Z( j* ~. ?+ OFor your reference.

0918429587

CAB_BS    LX28
: Z' ]5 r( ]& o& SCAB_BD   LX29

4 u, F9 ]" C9 x$ T9 l* S1 }$ S7 O其他我找不到
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
這是 CGDBO  CGSBO CBGBO

6 e  j3 Y& E: l: z5 [不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
5 P' Z0 l0 j0 k( }5 v% U9 FAn example for your reference...
8 `- V; V( m' V; B0 N; [8 |
" D0 L0 A+ U/ |----------------------------------------------------------------
9 f1 B. E/ G% Q; e***** Gate Capacitance Plots *****
.lib 'your_component_model' lib_corner
) W, }# J5 M% m  S5 m. G5 y.temp operational_temp
9 R6 V1 \& ~6 |4 Z% Z. ^# H( \.option dccap=1 post
m1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
vd n_drain gnd 0
; D- Y$ |& H, w5 d: H) Qvg n_gate gnd 5
6 Y. C* L! j  p+ w# P2 v0 ?vb n_bulk gnd 0
3 c  v6 S# ?: h) \! d: x( [.dc vd 0 5.0 0.1
.print   CGG=lx18(m1)
8 _% O) G7 p) L+        CGD=par('-lx19(m1)')
/ C$ U  s7 e4 ~, p4 s8 J+        CGS=par('-lx20(m1)')
' L/ L& X1 `3 X4 h8 U+        CDG=par('-lx32(m1)')
) j6 E& `: V, c' Q+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
! ^+ B; _4 q8 s2 q+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
.ends
: K# @; F( e3 y9 E+ {
. A1 `" h! Z: D, t* y% y----------------------------------------------------------------
Six capacitance are reported in the operating point printout
    cd_total = dQD/dVD
    cg_total = dQG/dVG
    cs_total = dQS/dVS
    cb_total = dQB/dVB
    cgs = -dQG/dVS
' T- ~0 W* b  a. `$ G    cgd = -dQG/dVD
8 V! b: N' l- |' J7 [There capcitances include gate-drain, gate-source, and gate-bulk
3 O4 K- z* u# O! y0 x: f+ {1 p+ Joverlap capacitance, and drain-bulk and source-bulk diode capacitance.
2 {) U( N1 O0 }4 C) v) }  [
+ f4 F: b7 x; i5 u" RCGG = dQg/dVG
CGD = -dQg/dVD
CDG = -dQD/dVG

The MOS element template printouts for gate capacitance are LX18~LX23
and LX32~LX34.

LX18(m) = dQG/dVGB = CGGBO
LX19(m) = dQG/dVDB = CGDBO
  [1 h* e3 ]- q3 ^LX20(m) = dQG/dVSB = CGSBO
6 H: R* ?4 q! Y4 w6 O6 E" N! O" b" L
LX21(m) = dQB/dVGB = CGGBO
LX22(m) = dQB/dVDB = CGGBO
4 P" D# ]# O6 p8 e& f. \LX23(m) = dQB/dVSB = CGGBO

LX32(m) = dQD/dVG = CDGBO
- }* f5 z4 E3 t* OLX33(m) = dQD/dVD = CDDBO
LX34(m) = dQD/dVS = CDSBO
  T6 A4 y; g- O( e# d9 Q' a( p
The equation shown above is for an NMOS with source-bulk grounded
+ O  H8 @3 k0 V9 p7 p! Mconfiguration. Refer to the user's manual for more detail ^^