hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs

要怎麼定義用
plot LX??
; x% P) F. c. b2 d0 g
$ i( E/ T) e- k: [5 K請各位幫忙一下

小朱仔

直接下.op及.probe
找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .
6 M* [7 P" z* R& g; a5 F0 T% O
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.


For your reference.

0918429587

CAB_BS    LX28
CAB_BD   LX29
  F. J2 }2 \& ~7 h2 ?$ U# W
其他我找不到
4 X, A; L8 x. g% |7 a! q( K5 T+ RCgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
% m" j  M, l6 {# {. X這是 CGDBO  CGSBO CBGBO

3 ]% F2 Z& p' o9 x" R+ w! G% h+ q" b不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
An example for your reference...

6 Z9 A. P- r! I8 D0 {* P* `" C----------------------------------------------------------------
2 ~; V' e$ S0 ?' K2 L***** Gate Capacitance Plots *****
.lib 'your_component_model' lib_corner
.temp operational_temp
.option dccap=1 post
m1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
vd n_drain gnd 0
vg n_gate gnd 5
; n* r0 y* z+ I! s! ?+ Tvb n_bulk gnd 0
# d- U  G6 e3 Z# n' }.dc vd 0 5.0 0.1
.print   CGG=lx18(m1)
% W) r3 g8 p, G% S7 [/ {- B& \5 {+        CGD=par('-lx19(m1)')
8 B, U3 I- ~' c9 P% R- Y+        CGS=par('-lx20(m1)')
+        CDG=par('-lx32(m1)')
+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
* B3 l" ^3 F8 O* S.ends

----------------------------------------------------------------
. W( }# s! F1 c' N/ q% oSix capacitance are reported in the operating point printout
& |$ |! W! b* }! K3 p  e    cd_total = dQD/dVD
    cg_total = dQG/dVG
    cs_total = dQS/dVS
    cb_total = dQB/dVB
    cgs = -dQG/dVS
- S# m0 e5 t! ?    cgd = -dQG/dVD
6 l6 f& m: T- f8 }( ]9 p0 yThere capcitances include gate-drain, gate-source, and gate-bulk
. L- F3 ~& i8 E9 Toverlap capacitance, and drain-bulk and source-bulk diode capacitance.
# [! O, {7 H7 }- F" e
$ W, t: |/ W9 u* w7 DCGG = dQg/dVG
* K8 Y9 d# U, A; C- K5 SCGD = -dQg/dVD
CDG = -dQD/dVG

% a9 p; @2 j; O/ n  vThe MOS element template printouts for gate capacitance are LX18~LX23
9 g! W  N8 V4 K2 h5 _and LX32~LX34.

LX18(m) = dQG/dVGB = CGGBO
LX19(m) = dQG/dVDB = CGDBO
. r4 i7 ~8 F  W7 dLX20(m) = dQG/dVSB = CGSBO
1 O8 v: n& v$ i+ F: i$ @9 W
LX21(m) = dQB/dVGB = CGGBO
, j+ S8 D/ q9 L; JLX22(m) = dQB/dVDB = CGGBO
LX23(m) = dQB/dVSB = CGGBO
) G; r+ Y  B/ ^9 c; Y
6 \! w% W1 M% S: ], b0 V) ]LX32(m) = dQD/dVG = CDGBO
! S7 c( @0 `/ k7 I3 M$ eLX33(m) = dQD/dVD = CDDBO
6 F# h3 ?- w4 ^0 Q8 h4 B$ N  k8 [LX34(m) = dQD/dVS = CDSBO

( d8 D2 r, e8 H( ?5 Y  v3 n2 LThe equation shown above is for an NMOS with source-bulk grounded
configuration. Refer to the user's manual for more detail ^^