hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs

要怎麼定義用
plot LX??
, {+ I$ U% V/ c; }; \& g+ y
請各位幫忙一下

小朱仔

直接下.op及.probe
找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .

Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.


For your reference.

0918429587

CAB_BS    LX28
CAB_BD   LX29
6 z+ C9 {7 j' U. z" _
) Q8 D8 Q; a! ~, u5 w其他我找不到
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
2 B* }$ g* N1 J! o* X3 Z這是 CGDBO  CGSBO CBGBO
) N* t, _/ l# j" b( G1 q
不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
6 K7 |4 i/ L5 m# M- }9 E. i: O# j0 T1 lAn example for your reference...
5 b6 y- n2 n+ Q, ?2 U( g
----------------------------------------------------------------
***** Gate Capacitance Plots *****
.lib 'your_component_model' lib_corner
3 `4 U7 p2 X3 p7 \, r1 E.temp operational_temp
.option dccap=1 post
m1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
' g2 e; O# {& Yvd n_drain gnd 0
/ S( U* G' }6 o, }2 Svg n_gate gnd 5
( s! P2 h) h# L- H# g: xvb n_bulk gnd 0
.dc vd 0 5.0 0.1
7 ?0 ], O0 O/ n- J* _.print   CGG=lx18(m1)
+        CGD=par('-lx19(m1)')
/ d. _1 L$ F2 [/ {: Y+        CGS=par('-lx20(m1)')
+        CDG=par('-lx32(m1)')
6 n, v4 b( s) P% C8 L+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
4 M, N+ j& r: `+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
.ends

----------------------------------------------------------------
% [. t5 b  v6 P2 nSix capacitance are reported in the operating point printout
    cd_total = dQD/dVD
' @. n- j; I6 X& N& D+ q5 z    cg_total = dQG/dVG
    cs_total = dQS/dVS
    cb_total = dQB/dVB
3 Y0 Z3 |7 j# r: I    cgs = -dQG/dVS
    cgd = -dQG/dVD
1 ~7 _+ q8 W/ n2 jThere capcitances include gate-drain, gate-source, and gate-bulk
overlap capacitance, and drain-bulk and source-bulk diode capacitance.

CGG = dQg/dVG
CGD = -dQg/dVD
CDG = -dQD/dVG
  m0 V( O7 F0 q7 u' [
: |4 z9 W* F- n) S# V7 n5 b5 ?The MOS element template printouts for gate capacitance are LX18~LX23
and LX32~LX34.
9 _3 w8 B- u# F4 c
LX18(m) = dQG/dVGB = CGGBO
+ x: n7 _3 }7 @7 {LX19(m) = dQG/dVDB = CGDBO
" Z5 k* [( r9 I8 V0 i3 I6 U) HLX20(m) = dQG/dVSB = CGSBO

LX21(m) = dQB/dVGB = CGGBO
/ M9 i* i9 e6 B* n* `2 pLX22(m) = dQB/dVDB = CGGBO
$ I7 I4 o# M) M4 A1 E0 Y6 \3 Z0 BLX23(m) = dQB/dVSB = CGGBO

" }/ ^7 [( A# @3 f( \( ~- V$ ULX32(m) = dQD/dVG = CDGBO
LX33(m) = dQD/dVD = CDDBO
& J1 s" o8 P* t: x* w2 _/ gLX34(m) = dQD/dVS = CDSBO

The equation shown above is for an NMOS with source-bulk grounded
) F* C! h& _8 H/ Uconfiguration. Refer to the user's manual for more detail ^^