hspice 問題 有關mos內部電容指令

0918429587

mos內部電容要看Cgs Cgd Cdb Cbs

要怎麼定義用
. }; N; u) ^- y& R+ Oplot LX??

請各位幫忙一下

小朱仔

直接下.op及.probe
% @* x7 Z- \6 Z2 l! J& J. _! O7 |! r找*.lis檔(模擬產生出來的檔)裡的MOS就可以看到您要的C值了

yalon

您得隨手  查一下 manual .
2 \2 r: G& N* K3 ]+ i9 F+ h
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out.


7 r+ v3 C' `& L0 j8 z& ]6 eFor your reference.

0918429587

CAB_BS    LX28
# I% X/ \2 }1 w% E  s6 T( S2 SCAB_BD   LX29

% n; u, ~% @% \7 U其他我找不到
Cgd Cgs Cgb 可由 lx(19) lx(20) lx(21) 分別 print out
0 b4 [) V8 }; d' m) Q: `5 w這是 CGDBO  CGSBO CBGBO
0 H+ u! w- H) S& S
不一樣

chcheng

Refer to "HSPICE User's Manual: Elements and Device Models Vol.II"
% w( F* L4 S# [+ f* o6 XAn example for your reference...
$ U& X' o! c7 j9 F, U
----------------------------------------------------------------
***** Gate Capacitance Plots *****
6 \* L" \4 G8 |8 Y. Y5 {: n, |.lib 'your_component_model' lib_corner
.temp operational_temp
.option dccap=1 post
m1 n_drain n_gate gnd n_bulk l=0.8u w=100u ad=200e-12 as=200e-12
% [$ K) _. |0 J& p/ X1 l, nvd n_drain gnd 0
/ h6 p/ w* j! J6 B% J( b, @vg n_gate gnd 5
3 T; V$ H/ ?; F5 N) svb n_bulk gnd 0
. I- t0 r2 I9 d3 g' {4 ?.dc vd 0 5.0 0.1
.print   CGG=lx18(m1)
+        CGD=par('-lx19(m1)')
) j; c' m# e/ h* Y/ b+        CGS=par('-lx20(m1)')
* g2 b  X! I" h8 q4 u  k/ g+        CDG=par('-lx32(m1)')
+        CSG=par('lx18(m1) + lx21(m1) + lx32(m1)')
+        CGB=par('lx18(m1) + lx19(m1) + lx20(m1)')
- M9 r: e) `+ m; Z9 V.ends

. K( {: R  E& ]2 C----------------------------------------------------------------
Six capacitance are reported in the operating point printout
/ m6 k: B  M# P    cd_total = dQD/dVD
9 \& Q0 j: y) b6 Y! r    cg_total = dQG/dVG
# t% x/ A/ w0 `; B    cs_total = dQS/dVS
    cb_total = dQB/dVB
    cgs = -dQG/dVS
8 s; m$ W1 Y6 p* l( b    cgd = -dQG/dVD
6 ~: J& m+ Y* L; ~. sThere capcitances include gate-drain, gate-source, and gate-bulk
; t7 g, k+ M, k+ @' Hoverlap capacitance, and drain-bulk and source-bulk diode capacitance.
) ?" N/ R" J* T/ @. c  m
CGG = dQg/dVG
" S1 G* e* ~/ u4 \CGD = -dQg/dVD
5 L3 C; Q1 }3 c- fCDG = -dQD/dVG

( w' x6 N- o2 {0 j6 t) R/ I$ z$ oThe MOS element template printouts for gate capacitance are LX18~LX23
1 ~/ j2 I- L! [, \( n8 fand LX32~LX34.
6 a7 U% m' U! q9 V3 |! z# l0 z
& n/ Z( b" ~" L2 N& O# N4 S9 MLX18(m) = dQG/dVGB = CGGBO
LX19(m) = dQG/dVDB = CGDBO
LX20(m) = dQG/dVSB = CGSBO
1 o% M: v0 y* j. y, q) j
LX21(m) = dQB/dVGB = CGGBO
: q3 m% z  n( B: `0 Z3 CLX22(m) = dQB/dVDB = CGGBO
! z% s2 Y/ W2 e) e! gLX23(m) = dQB/dVSB = CGGBO
( P# p6 ], g+ D. Z8 h) |+ G
LX32(m) = dQD/dVG = CDGBO
6 c) M3 K0 }: t+ ]4 nLX33(m) = dQD/dVD = CDDBO
LX34(m) = dQD/dVS = CDSBO

The equation shown above is for an NMOS with source-bulk grounded
configuration. Refer to the user's manual for more detail ^^