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回復 4# 的帖子
1. Using technology file to create a library
: h5 \& G$ v1 ?0 W6 x0 A1 H2. Do stream in with cell type definition file. Specify some special layers' number. IE : Boundary Layer is 63.
6 [9 g: n5 _; J3. Open new created library, and create some metal blockage if need.% p! D- c" t$ f. d; P4 T
4. Do smash if need.% n8 n) R6 ?: n/ y2 a8 c* O
5. remove some unnecessary extension txst. IE VDD ---> VDD
0 r6 a9 ^: L1 a# i- W+ E6. Define power,ground as well as in/out port
8 K6 g1 c6 I) \% n* a7.Extract Blockage,Pin and Via by using command auExtractBlockagePinVia.
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% o; {' q* A5 B) m5 eThe processes listed above is my method to do data preparation. Maybe someone know other best way for this issue. Please share it with us.- S" D8 |1 F3 G
-->我要怎麼做才可以把 ANALOG中 重複性較高的部份交給 APR去做?' W5 _; `+ [$ h: _
I don't understand your question. Do you want APR toll to place and route your analog block? It is a bad idea if your answer is yes. |
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