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我目前在設計一個pipeline的電路,且有防bubble機制,但在設計的過程中有些問題~
* R5 ^( ^& C n& {1 K) a/ `想請問一下大家!!/ D$ w% ?% j+ A) i
該怎麼設計?2 w2 \: J, |3 V. ^6 a. |
以下是我需要的功能~
! r d; ?1 B! F9 E4 K' e3 D- y | | | | | | | | | | | | | | | | | | | The next stage data full signal | | | | | | | | | DUT full signal to preceding stage |
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Thereare 5 pipe stages in our pipelining design. # v8 O" q" \. q/ `7 O9 X
It means that the input data can beobserved at the output port after 5 clock cycles. ! S% O2 b$ r5 ?( h4 ~: G
All the stages must be readyto proceed at the same time.
" j$ X) x' A8 j) b3 h$ JWhen d_full is active, you have to keep the outputdata until d_full is disabled.
, K9 ~* H+ @0 Z( OIf d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data. t& Q' e# s+ E! E6 R9 C8 ^, B
The pipeline bubbles haveto be eliminated when d_full is active.; L; \6 `8 ~0 J8 w. ?4 @
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