[急]verilog pipeline bubble 設計

HsuanChihCh@FB

我目前在設計一個pipeline的電路，且有防bubble機制，但在設計的過程中有些問題~
! ~6 T  p$ \2 l% ~. b6 z; j想請問一下大家!!
該怎麼設計?
, x) y( Y. {; t" m! r7 g以下是我需要的功能~

Module name	my_pipeline
Signal	Direction	Description
clk	input	System clock
rst_n	input	reset signal, active low
d_in[15:0]	input	DUT input data
d_rdy	input	DUT input data ready
d_full	input	The next stage data full signal
pp_d[15:0]	output	DUT output data
pp_rdy	output	DUT output data ready
pp_full	output	DUT full signal to preceding stage

Thereare 5 pipe stages in our pipelining design.
It means that the input data can beobserved at the output port after 5 clock cycles.
All the stages must be readyto proceed at the same time.
2 O4 a# n  s+ ~6 f7 BWhen d_full is active, you have to keep the outputdata until d_full is disabled.
If d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data.
$ ]9 Z' [4 k' \The pipeline bubbles haveto be eliminated when d_full is active.

6 T4 \4 `. L% }  x$ L
$ [) ?) Z* T. u  B. i" b) ]

. M2 o' P. A" W& z

4 z4 u5 G. H( n
1 `  _0 \  c0 E+ ?, ^3 |* {: p
: a9 |7 j+ G0 r) M+ S+ u# a- u
9 \) ~$ R6 m( Z* g2 C

2 q2 [3 ?- |' d( z
2 q1 G3 R4 X7 x5 t$ V- G1 m3 z- ~



1 T# ]" l3 y0 r4 a
# S' b6 x1 ]+ }) t
" c. b  W- Y; K# ^' f2 h. |( H