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我目前在設計一個pipeline的電路,且有防bubble機制,但在設計的過程中有些問題~- ]/ y0 H8 z" X6 h, Q! ^* r
想請問一下大家!!
' y7 S% Y3 \) a該怎麼設計?2 v7 B) f. ?/ D3 N9 u; W
以下是我需要的功能~% x' M5 e& }# [2 ?
| | | | | | | | | | | | | | | | | | | The next stage data full signal | | | | | | | | | DUT full signal to preceding stage | : X$ ]; o( W" V: _$ o% t
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Thereare 5 pipe stages in our pipelining design. ; S* [2 Y( Z# P
It means that the input data can beobserved at the output port after 5 clock cycles. @1 e" E; }2 X! T" `- e
All the stages must be readyto proceed at the same time.
5 |& U: N2 ]; K, I+ z# Q( y7 Q7 _( HWhen d_full is active, you have to keep the outputdata until d_full is disabled.
3 \; @) F/ K" q" \, g8 `If d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data.
6 j. @' y! h1 {& b5 b, uThe pipeline bubbles haveto be eliminated when d_full is active.
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