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我目前在設計一個pipeline的電路,且有防bubble機制,但在設計的過程中有些問題~& W1 @; S9 v" I* Y
想請問一下大家!!
5 J J+ E# r% Z. e該怎麼設計?
7 ?" u" t! {5 z0 T" t) F以下是我需要的功能~! a+ I9 ~; ]& T4 w8 K0 `, O
| | | | | | | | | | | | | | | | | | | The next stage data full signal | | | | | | | | | DUT full signal to preceding stage | 6 d% D; f5 i/ V: G
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! i7 n! l$ U4 sThereare 5 pipe stages in our pipelining design.
, [. U, Q- Y1 v+ P% xIt means that the input data can beobserved at the output port after 5 clock cycles.
2 k: G7 q2 u" }All the stages must be readyto proceed at the same time.
1 h' o$ i8 `* F- S1 AWhen d_full is active, you have to keep the outputdata until d_full is disabled.
2 i5 g/ K* E* EIf d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data. + Q) |0 h( f9 J" N. c
The pipeline bubbles haveto be eliminated when d_full is active.# W" V; A; K' ~5 T
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