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我目前在設計一個pipeline的電路,且有防bubble機制,但在設計的過程中有些問題~% V! u' ^4 d$ v6 D6 G
想請問一下大家!!, l4 B& u6 l+ ?# i$ D, H# p
該怎麼設計?7 ^1 D$ |' ~2 C
以下是我需要的功能~
* b: T9 i+ h1 A9 f | | | | | | | | | | | | | | | | | | | The next stage data full signal | | | | | | | | | DUT full signal to preceding stage | : w u4 K+ O4 z/ v8 u5 X
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: W2 S# K* E/ _0 lThereare 5 pipe stages in our pipelining design. 6 b1 J" G- I( F7 ]: a7 V
It means that the input data can beobserved at the output port after 5 clock cycles. 1 D4 y p0 _) a+ D" R5 [' f+ R
All the stages must be readyto proceed at the same time.
4 O! ~& H* ?, v4 o; bWhen d_full is active, you have to keep the outputdata until d_full is disabled. 3 z. n/ O+ V, X" Z
If d_full is active and all the pipe stages arebusy, you have to generate pp_full to inform the preceding stages to hold data. & E( x, `5 k/ K0 h( |1 e- x
The pipeline bubbles haveto be eliminated when d_full is active.
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