verilog clock generator question

jyunwei

Hi

6 o6 e# D+ q2 X2 _) X; NMy clock generator is as follow

`timescale 1ns/10ps

`define period 15
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7 l5 W: Q; _# h0 Fmodule test();
reg clk;
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initial begin
clk = 0;
; \7 g8 h$ T9 T4 F5 qforever #(`period/2) clk = ~clk;
! \2 K# S& X" ?7 b9 Cend
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But i check the waveform the clock period is always 14ns.
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6 c+ O5 I( a1 L3 d5 }0 d0 \Could anyone help me the question ?

Thanks
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