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Senior Physical Design Engineer3 T5 b# X4 `9 X/ q/ ?
公 司:A famous IC company
* R5 Y$ k( ^1 p$ z( e/ _; \工作地点:南京( q; D- S: p; e/ O( s$ \$ x9 z M
! t; |0 h9 e+ _; `$ ^+ |Key Responsibilities ) \3 q% N4 b# O/ H' ?; n
Depending on experience, key responsibilities will involve some of the following:
& ]* ?' J, Y* p0 NIC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification.
1 v) ~/ j7 F9 a+ t* V, r- ZAs a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
( f0 Z. T7 ?2 qLeading a team of physical design engineers and resolving the technical related issues. 3 }' a, t, `1 @' N, [
Crosstalk analysis, power analysis, and static timing analysis. : p$ [) X& ~& m9 K& s- \
Write scripts in Tcl to improve productivity. + T o$ e1 n0 i% N; g
! j$ B0 ~8 [% m' X( r6 I) `. O# N% ~Experience: 5+ years in physical implementation engineering 2 ^1 H2 N# k: v' L( y, s) j
' D/ l2 u9 |! rEssential skills
, j7 N4 k5 ^# WMS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills
% u! E- ^% y+ |9 A: I4 K1 ?, WExperience with Magma or Synopsys place-and-route tool set and physical design project implementation.
+ t, K ^$ y7 hGood programming skill. Capable of writing Tcl or Perl. 7 a& b; ` b- [" I; u- z
Familiar with synthesis, static timing analysis.
) ?2 W4 `* L! A/ P8 t* DSelf-motivated team worker, good verbal and written communication skills in English.
0 ?. x( H+ o8 TTechnical and team leadership proffered. Previous management experience highly desired.
' y N& ` {' [% }* ]; ZExperience with synthesis, DFT, and verification is preferred. |
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