|
Senior Physical Design Engineer5 B* M8 K3 H2 \2 E$ Y+ E
公 司:A famous IC company5 b2 s8 u( E$ z& K
工作地点:南京
6 }4 Q7 z/ X8 f7 c" o3 A j1 H) q" ]
Key Responsibilities 1 U6 t% `6 z1 X+ D- [3 g4 S
Depending on experience, key responsibilities will involve some of the following:
$ J1 i' l5 W; l+ kIC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification. / x6 F) W4 Y3 E9 b3 q; M( P- T5 T$ g
As a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
3 V7 z) H& n+ L2 o3 O9 gLeading a team of physical design engineers and resolving the technical related issues. 1 R6 V, |% b2 k- F7 m; ?6 d
Crosstalk analysis, power analysis, and static timing analysis.
; O. r+ t' U7 KWrite scripts in Tcl to improve productivity. # R; k2 {- \2 h$ i3 b) H4 j6 L
4 G* g5 S. `- K$ A) a, BExperience: 5+ years in physical implementation engineering
3 ^) k, I1 b& R4 n) `
3 t! ~9 I; a V- t/ n* d! MEssential skills & J9 \ O, Y' O+ @ `( t) A
MS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills 8 l. \5 t3 V. Z+ R" w1 y* ?9 N
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation.
) o( P0 n2 e8 iGood programming skill. Capable of writing Tcl or Perl.
! e# V2 y k: J# r$ Z% @Familiar with synthesis, static timing analysis. 2 U' _% C( U! t5 C( _% s: x3 W
Self-motivated team worker, good verbal and written communication skills in English. : x6 K: G/ |) Y1 { G3 B) }: D
Technical and team leadership proffered. Previous management experience highly desired.
/ e5 _! _; G8 p) I2 YExperience with synthesis, DFT, and verification is preferred. |
|