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Senior Physical Design Engineer6 _. V- T, t! l% U1 X4 V6 P
公 司:A famous IC company
! A% i8 x: m0 l0 ^4 e8 t0 ]工作地点:南京
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7 O2 v0 U7 M( f3 h( |: tKey Responsibilities
6 h6 k# k' q8 v5 ]Depending on experience, key responsibilities will involve some of the following: v8 `' |! v1 V4 l+ u9 u
IC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification. % |% ]' F2 T! I8 u l
As a key member of physical design team, your will work on one of most advanced and the most complex chip designed. 3 \% ]: Y$ O( h9 B! D: X; l
Leading a team of physical design engineers and resolving the technical related issues.
+ C7 U* ]4 j' |. ECrosstalk analysis, power analysis, and static timing analysis.
* M, _3 r9 B/ q/ pWrite scripts in Tcl to improve productivity. ) Q0 r% J# H- O6 G% v
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Experience: 5+ years in physical implementation engineering
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' _9 [# l9 p. ~% U G3 m6 ZEssential skills 5 U: ~7 d6 I+ I ^' L; `" N9 w U
MS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills
" l/ S7 |; ?+ \5 q9 XExperience with Magma or Synopsys place-and-route tool set and physical design project implementation. : Z" q7 ]$ E& V0 N+ u0 a9 R
Good programming skill. Capable of writing Tcl or Perl.
- \& j# R6 l$ J1 W TFamiliar with synthesis, static timing analysis. " L; c& b; ?8 T/ \
Self-motivated team worker, good verbal and written communication skills in English.
) R5 t0 Y5 \. w" X- B; jTechnical and team leadership proffered. Previous management experience highly desired. 7 S7 ]( K" j8 O1 M K. J$ h
Experience with synthesis, DFT, and verification is preferred. |
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