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發表於 2013-12-12 09:14:21
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Senior Physical Design Engineer. h2 ]% j( C Q8 o+ u+ I \4 @
公 司:A famous IC company+ c$ Y& S% U* P0 t( N3 a# t
工作地点:南京: Z8 U' l+ ?+ [5 k1 D" C# ?
7 W% o& R0 e! k/ z' S D* {- tKey Responsibilities 4 e) x3 {% t& u8 h- g9 W$ ^! U
Depending on experience, key responsibilities will involve some of the following:
5 V/ @" s! }' z, S1 Y8 n; PIC implementation from netlist to gdsii, with synthesis, floorplanning, place and route, timing closure, and physical verification.
7 y' w1 }- | ZAs a key member of physical design team, your will work on one of most advanced and the most complex chip designed.
4 H" I, @& U0 H* t. O; ^4 cLeading a team of physical design engineers and resolving the technical related issues. $ `1 }& A+ e7 E" w
Crosstalk analysis, power analysis, and static timing analysis.
0 \+ Y8 P( E( L+ ?: iWrite scripts in Tcl to improve productivity. " o1 l$ E5 q% V" o& v v
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职位要求* A p# x* P; s& e% \0 ^+ u
Experience: 5+ years in physical implementation engineering 8 ?& {- {8 h+ y; g `- Y1 M/ b) x1 \
Essential skills
8 l$ T! i: j, \( j7 ~: nMS in EE required.&#8226roven track records of working independently on place-and-route project running and DRC/LVS/ERC/Antenna debugging skills ( i5 Y7 @2 ]0 W4 \
Experience with Magma or Synopsys place-and-route tool set and physical design project implementation.
3 N/ }, ]% r$ |( YGood programming skill. Capable of writing Tcl or Perl.
: d2 f8 C7 K) MFamiliar with synthesis, static timing analysis. # `& G8 x* ~3 R" @
Self-motivated team worker, good verbal and written communication skills in English. 9 r( z# ?5 ~6 D- q: i
Technical and team leadership proffered. Previous management experience highly desired.
/ @# ~ `. P2 R' t2 s3 c: |# HExperience with synthesis, DFT, and verification is preferred. |
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