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FPGA verification Engineer most difficult job functions?

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1#
發表於 2011-7-18 17:19:12 | 顯示全部樓層 回帖獎勵 |倒序瀏覽 |閱讀模式
招聘公司:A famous IC company1 y. Y+ p# x  D. d+ d- z" }' h
招聘岗位:Senior FPGA verification Engineer
# T7 M1 b5 L2 U! Q* W; T工作地点:Shanghai
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1 g5 G  I$ I: i! G3 h( [岗位描述:
" i1 {, g5 g3 [, h, TJob Responsibilities 1. Port whole chip to Altera Stratix4 FPGA development board 2. Anticipate the HW/SW co-simulation environment building 3. Help debug the IP such as DMA, Memory controller, Display Unit; ^& s3 a+ Q' H' y' h

" T7 o9 ~+ b2 W职位要求:' b* f) I4 @7 J5 X; {) s$ ]& a( _
Job Qualification 1. CS or EE Master is preferred, 3~5 years of relevant experiences 2. Altera FPGA verification experiences 3. Familiar with Altera Sigal TAPII 4. Familiar with Oscilloscope, Logic analyzer 5. Familiar with ARM SOC 6. Familiar with Verilog or VHDL2 G7 D6 ~5 v% @5 d

3 V' p7 q, D# w& f# {9 v. \( _能者與意者請email研發簡歷與chip123聯絡。
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2#
 樓主| 發表於 2011-7-22 12:07:24 | 顯示全部樓層
招聘公司:A famous IC company. b& I) n" k. j6 e' j9 f. p
招聘岗位:Firmware Verification Engineer (Enterprise & Storage Division)& D  ?& U1 r, D
工作地点:Shanghai
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岗位描述Job description:
: @# o" C1 W- ?- ZAs a Firmware verification engineer, you will join a rapidly growing team of professionals in the development and verification of real-time firmware for storage ASICs. Your initial responsibilities will include, but are not limited to the following:
* {( n/ n9 j1 N6 T4 O5 |5 j9 D- Z% S Collaborate with global and local teams to verify the full storage system solution.
& e& A' D) `! C/ M Analyze technical requirements and Firmware designs to create the verification test plan * |) O7 J, y0 K3 k6 h9 i
Develop the test cases including both system level and to interfaces. $ r  G! G& ?( v1 u) Q
Execute the test cases and debug the issues found as well as provide comprehensive analysis.' k2 u8 P1 N, b& U5 p. o2 C# t9 G2 N
Log bugs found to tracking system and follow up till the end of life0 s4 j* e) Q2 ~9 u5 G
Participate in specification, design and implementation review with peers.
4 T, O) D" o) W; Z Use of storage testers, analyzer and other debug tools.
' `4 L# \3 G+ |6 d( }3 d Write and review engineering documentations" [; n, u, c3 C6 u% R4 P
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职位要求Qualification:! B* D. h2 c. G$ {4 S. g. t
Master or Bachelor’s degree in Electrical Engineering or Computer Science  z1 j8 P4 G. B, f( [& `* {% J
3+years of Firmware development or test experience: F+ _* v/ `" x8 z" \0 Z0 Y! r
C language programming and debugging( ^& ^* L. C; f4 t  @2 ]
Skills of script language programming, such as Perl, Tcl/Tk, or similar: [. ]& D9 M/ a
Solid knowledge on Linux kernel or device driver or tools.
/ }: C& P- _( w1 {/ F1 B! d6 L Master test process, and experience on test tools and test cases development
) A+ o9 l2 p* t* S Familiar with storage specifications, especially SCSI, SAS, SATA, and PCI Express are plus.
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3#
 樓主| 發表於 2011-7-22 12:16:43 | 顯示全部樓層
招聘公司:A famous IC company3 k2 q' x! }5 P8 O
招聘岗位:IC logic design engineer
0 }+ i5 z+ s9 q" s" X: H工作地点:shanghai
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7 y, X* B4 ^: i( ~% m岗位描述:
6 B7 [1 A1 E; J+ x8 ?Job Duties: Micro-architecture design, RTL coding, simulation and verification of the assigned graphics block; should be also responsible for the synthesis and timing check of the block.
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职位要求:Qualifications: (Educations, Experience, etc.):
: B7 C/ G5 C* l$ W' ?1.Education: Master degree or above, major in Micro-electronic,EE, CS or related.* o/ f6 r7 Q# F6 m/ E* x& I# i
2.Experience: Have experience on SOC chip design.3 ?$ c& m' L4 c, G  J1 x8 x4 N/ j+ u
3.Knowledge of/Skills and Abilities
; W! P# U3 W% D' ^3 m" e$ ?3 V  d4 b8 r·Be familiar with IC logic design flow;2 ]1 U# h% m" k2 C/ F) O
·Have good skill in RTL coding, simulation, synthesis and static timing analysis;
' T8 j6 s* D* R6 u·Have strong hardware knowledge of computer architecture, Know-how in computer graphics is preferred;$ t9 `6 C% H! W0 }; `
·GFX Chip design experience will be a good pls.
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