FPGA verification Engineer most difficult job functions?

mister_liu

招聘公司：A famous IC company
" }/ f3 i( F- ~6 i) ]* P招聘岗位：Senior FPGA verification Engineer
% N  y& Q9 O- `7 N* i) b: a工作地点：Shanghai

1 W5 o; M: p0 V. H0 j4 r' l9 @岗位描述：
Job Responsibilities 1. Port whole chip to Altera Stratix4 FPGA development board 2. Anticipate the HW/SW co-simulation environment building 3. Help debug the IP such as DMA, Memory controller, Display Unit

9 C% N  i( U2 x) [! b职位要求：
Job Qualification 1. CS or EE Master is preferred, 3~5 years of relevant experiences 2. Altera FPGA verification experiences 3. Familiar with Altera Sigal TAPII 4. Familiar with Oscilloscope, Logic analyzer 5. Familiar with ARM SOC 6. Familiar with Verilog or VHDL

能者與意者請email研發簡歷與chip123聯絡。

ranica

招聘公司：A famous IC company
工作地点：Shanghai
# W0 g  l$ [( g' a) V& B" @
; q: \& P+ P3 l% K5 q" z岗位描述：
  d# S+ w$ u' }( M1 i& }1 fJob Responsibilities 1. Design AXI NOR flash controller, AXI SDRAM controller 2. DDR2/DDR3 IP integration and verification 3. FPGA DDR2/DDR3 PHY integration 4. Write test plan on memory controller 5. Write C test cases to memory controller 6. Be responsible for all the techniques of memory controller

; @+ y* k0 w, b  b1 F" o) l职位要求：
Job Qualification 1. CS or EE MS/BS , 3~5 years of relevant experiences 2. Verilog or VHDL, C language 3. Familiar with memory controller including SDRAM, DDR2/DDR3 4. Be familiar with AXI, AHB, APB protocol 5. Assertion , Random test and coverage knowledge

能者與意者請email研發簡歷與chip123聯絡。

ranica

招聘公司：A famous IC company
工作地点：Shanghai
9 g+ _$ c$ |3 u" n; i
* j' C4 _* s3 k6 H# ?岗位描述：
* r# L7 X4 `1 |Duties • IP design and support for digital baseband of cellular phones • Digital SOC design and integration for chips
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3 o+ l5 R0 I6 S9 t3 G+ s0 d! @职位要求：
Requirements • B.Sc. degree or above in Semiconductor, Electronics Engineering areas • 2 years or above design experience in industry • Good knowledge of design flow including documentation, VHDL/verilog coding, code check, equivalence check, synthesis, timing analysis and RTL simulation. • Good knowledge of AMBA AHB/AXI protocol is preferred. • Good knowledge in UPF/IP-XACT based design flow is a big plus. • Hands on experience in digital IC design EDA tools, such as NCSim/Questasim, Design Compiler, Formality, Primetime etc. • Good communication skill, will have frequent communication with foreign teams. • Good written and spoken English is mandatory.

9 C; S$ y0 U' ^能者與意者請email研發簡歷與chip123聯絡。

tk02561

招聘公司：A famous IC company
招聘岗位：Architectural Design Verification Engineer
工作地点：Shanghai

岗位描述：
Responsibilities: To develop assembly programs for testing the compatibility of CPUs with the XX architecture. To develop and extend Perl programs which automate the creation of these assembly programs. To work with CPU architects to develop and implement test plans for the verification of new and existing XX architectural features. To work with simulator and core developers to run these verification programs, debug failures and identify necessary fixes to the models, cores, simulators and architecture

职位要求：
Knowledge/Skills: Excellent programming skills and proven programming experience (post-graduate level research in a programming intensive field, or 3 years of industry experience) Excellent problem solving skills Ability to work independently, contribute to team goals, and to work with other team members in remote locations The following skills will be used on the job. Candidates with outstanding, proven programming experience in other engineering or scientific research fields would be given the opportunity to learn some or all of these skills on the job: - Knowledge of XX architecture - XX assembly language programming - Perl programming - Development experience in the linux environment Requirements: Education : BS in EE or CS (MS or higher preferred). Experience : Four years experience or more in related area. Systems : Unix, Linux, Windows. Language : Good English verbal skills plus reading/writing for documentation. Spirit : Good team spirit, professional, motivated and eager to learn combined with natural curiosity "to discover", "to know" and an attitude "to fix a problem".
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能者與意者請email研發簡歷與chip123聯絡。

tk02561

招聘公司：A famous IC company
招聘岗位：CPU Core Design Verification Engineer
工作地点：Shanghai

3 l  ~9 U. p! G: KResponsibility:
; O7 D" L3 S# t$ rDevelopment and verification of XX microprocessor cores and products.

8 p" m8 y. x7 P: s& h3 W1 Z& |3 k9 TKnowledge/Skills:
4 B$ j. b+ ]0 S" H! v5 WStrong microprocessor architecture and micro-architecture knowledge.
$ v( S2 _) c" f4 h: d! x1 R% B8 rUnderstanding of XX architecture is preferred.
. D# f; k7 B" e! W' RGood logic and RTL design skills.
+ k& R' l& ^* o6 k  S% `Experienced with CPU design verification, debug, and testing methodologies.
Good knowledge of common test methods and techniques (ie: regression, functional, random, structural, emulation ...)
Experienced with building test environments, test benches, checkers, test vectors, assertions, coverage analysis, ...
Good programming and scripting skills, such as Verilog, System Verilog, assembler, Perl, Shell scripts, C, TCL, Windows Office, ...etc

2 a0 y3 L; J/ kRequirements:
Education : BS in EE or CS (MS or higher preferred).
Experience : Four years experience or more in related area.
Systems : Unix, Linux, Windows.
Language : Good English verbal skills plus reading/writing for documentation.
Spirit : Good team spirit, professional, motivated and eager to learn combined with natural curiosity "to discover", "to know" and an attitude "to fix a problem".

能者與意者請email研發簡歷與chip123聯絡。

mister_liu

招聘公司：A famous IC company
2 G" c! H" V& |2 f1 J% b% Q  G招聘岗位：Firmware Verification Engineer (Enterprise & Storage Division)
. c( D6 P& d; D, B; g( }8 a: e工作地点：Shanghai
8 \% u& |! k5 h
岗位描述Job description:
8 V7 @7 z0 B, y1 A- l+ ~As a Firmware verification engineer, you will join a rapidly growing team of professionals in the development and verification of real-time firmware for storage ASICs. Your initial responsibilities will include, but are not limited to the following:
7 }( d' o0 W! d- D; R/ J4 a  G Collaborate with global and local teams to verify the full storage system solution.
Analyze technical requirements and Firmware designs to create the verification test plan
Develop the test cases including both system level and to interfaces.
' k5 ~3 A( W7 Z3 p# b! PExecute the test cases and debug the issues found as well as provide comprehensive analysis.
' J8 z8 w0 I; s( o7 U& ? Log bugs found to tracking system and follow up till the end of life
% o6 |* o: h. t9 F4 Y5 g Participate in specification, design and implementation review with peers.
Use of storage testers, analyzer and other debug tools.
Write and review engineering documentations
4 N1 E4 u& u0 W  k$ J. K( }) H
职位要求Qualification:
$ y+ {. Y& W/ M1 y7 T! v+ Z Master or Bachelor’s degree in Electrical Engineering or Computer Science
3+years of Firmware development or test experience
C language programming and debugging
# w4 T. l. w/ }0 }6 d' Q Skills of script language programming, such as Perl, Tcl/Tk, or similar
' ^* C. ]& q2 L- @6 B Solid knowledge on Linux kernel or device driver or tools.
: b) B( A# r) P2 ? Master test process, and experience on test tools and test cases development
Familiar with storage specifications, especially SCSI, SAS, SATA, and PCI Express are plus.

mister_liu

招聘公司：A famous IC company
招聘岗位：IC logic design engineer
工作地点：shanghai

  f4 `  {$ z# G. p* h岗位描述：
Job Duties: Micro-architecture design, RTL coding, simulation and verification of the assigned graphics block; should be also responsible for the synthesis and timing check of the block.
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职位要求：Qualifications: (Educations, Experience, etc.):
% k/ L3 d) @) d3 |3 _1.Education: Master degree or above, major in Micro-electronic,EE, CS or related.
2.Experience: Have experience on SOC chip design.
' i: h, S/ Z, O" l4 v, U. t3.Knowledge of/Skills and Abilities
·Be familiar with IC logic design flow;
·Have good skill in RTL coding, simulation, synthesis and static timing analysis;
4 k* a( j. i/ f( o$ v·Have strong hardware knowledge of computer architecture, Know-how in computer graphics is preferred;
·GFX Chip design experience will be a good pls.

ranica

招聘公司：a top 15 semiconductor company
招聘岗位：Senior Digital Design Verification Engineer
工作地点：Beijing
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$ F. s, C4 |, f( _% H4 K& [岗位描述：
Job Description Responsibility: The responsibilities include but not limited to: 1. Leading the high efficient verification platform development for application specific digital processor system and the whole chip digital system. 2. Leading the high efficient mixed signal verification platform development for mixed signal chips. 3. Work together with local and US team to define the verification strategy, test plan and quality benchmark. 4. Work together with local and US team for system validation. 5. Digital micro-architecture design, RTL design and implementation.
/ r+ O$ Q  ]+ ^
$ [# i+ D2 q0 c6 r' H1 b6 o$ Y职位要求：
Requirement: 1. MSEE or PhD in EE or microelectronics or computer engineering. 2. 3 year+ experience for MSEE and 1 year+ for PHD on digital verification, RTL related design and implementation. 3. Proficient in SystemVerilog and advanced verification platform development (VMM/OVM/UVM/etc.). 4. Be familiar with SoC design and verification methodology is preferred. 5. Be familiar with digital signal processing for image processing or communication is preferred. 7. Good spoken and written English. 8. Self motivation, result oriented, good team work and communication skills.

ranica

招聘公司：A famous IC company
招聘岗位：Design Verification Engineer, Staff
工作地点：Shanghai
2 X' O7 f: l4 Z6 `1 B! w$ p3 r
岗位描述：
Job Function This DV Manager will be part of a team working on the future integration of complex SOC and switching product. The successful candidate will play a key role in driving many of the key DV architectural and in depth technical aspects of various projects and perform the following duties: - A multidisciplinary function, working in close collaboration with the design engineering teams and managers and directors on the various efforts involved in the definition and implementation of various projects and scoping development efforts and project schedules. - Responsible for the overall chip verification, in addition to the possibility of direct responsibility for the architecture of specific IP blocks or functions, depending on any specific area of expertise the candidate might have. - Interacting with and guiding a wide variety of internal and external design verification development teams, DV methodology, silicon IP and tool vendors. - Work with senior management, architects, and the design and DV teams across sites to contribute in definition of ASIC products specifications, feature definition and architecture.

ranica

职位要求：
Skills/Experience - 10+ working experience in the field of design verification, experience in networking or switching design is a big plus. - 3+ years as DV technical lead/architect or manager position. - Proven experience of the latest design verification methodology such as OVM, assertion based coverage driven verification (code & functional coverage), constraint random test generation, formal checkings, power verification, modern design verification tools and languages (e.g. PSL/SVA, SystemC++, SystemVerilog, Vera, Specman, simulation systems) - In depth experience in use of SystemVerilog and OVM to drive testbench is highly desirable - In depth knowledge of ASIC design fundamentals from RTL to GDS including DFT verification. - Experience in power verification is a plus. - Proven debugging and problem analysis skills. - Strong documentation and communication skills. - Good people and project management skills including scheduling, resource allocation, risk assessment, matrix management, and process development and organized and methodical with proven ability to plan and execute project. - Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites North America and Asia - Flexible in terms of responsibilities and hours. Education Requirements MSEE or PHD in EE or CS

ranica

招聘公司：A famous IC company
/ ?2 [7 F: p5 I  ~: k' S4 a, z招聘岗位：Lead SW Integration and Verification Engineer
工作地点：Shanghai

岗位描述：
Job Description S/W Integration and Verification engineers will be responsible primarily for defining the requirements for system and software test based upon system requirements specifications and preparing for detailed, comprehensive test procedures. Key responsibilities will include validation of S/W package as well as integration with GUI, DLL, COM, and device driver. Applicant must be comfortable with quickly learning new technologies, have strong design and problem solving skills and must be a team player.

职位要求：
+ `* w* ]: W6 J% s8 |: s3 _& ARequired Skills - Bachelor or above of Software / Computer Science or equivalent experience. - Minimum of 4 years of SW verification expereicne or equivalent. - Strong knowledge of at least 2 of the following scripting languages such as Perl, Python, VB script, DOS batch file, or Unix shell script. - Must be proficient in authoring and updating test plans with raw data, and summarizing results with simple spreadsheets or complex/custom data analysis tools. - Experience in each of the major testing types comprising a test cycle including functional, system/integration, regression and error handling. - Create, maintain and execute automated tests using script languages. - Proficiency with scripting languages, compiling, and debugging builds for C/C++ applications. - Strong verbal and written communication skills. - Exposure to the entire software development life cycle. - Utilization source control tools such as Visual Source Safe to establish proper version control of automation scripts and to build the S/W package for integration. - Understanding TCP/IP Network stack is a plus. - HTML, SNMP, or XML Experience is a plus.

ranica

招聘公司：A famous American IC company
招聘岗位：Sr. Staff ASIC Verification Engineer / SOC Verification Lead
工作地点：Shanghai

3 T3 U  s5 o& D4 }, [( j3 j岗位描述：
Job Description:
  j. W8 l2 M: k! t7 D9 Q7 N: yAs a core member of a XX China SOC development team, primary responsibility will be verification environment development and verification planning and executing. Lead the verification group to accomplish SOC project verification tasks.

5 J$ ^/ y; D& [8 h- O8 M% I5 F' SSummary of Duties/Responsibilities:
· SOC verification requirements analysis and planning
. M( B8 \2 Y, B- f; W6 Z· Architect and build OVM based test environment for efficient and flexible IP level and SOC full chip verification
: D1 k% |7 p2 }& r6 }  s; P· Create test plan, and lead the verification organization to implement the verification tasks
· Design coverage metrics and verification reporting system
, m( l# V' t7 m' Y9 B, Y, w& k9 a· Coordinate debug efforts to achieve IPs and full chip functionality
( s& g% k- n7 C* h; D· Documentation of verification, organize/participate in verification/design reviews

ranica

职位要求：Job Requirements:
# v: O' Q$ o* {: g: b* T3 ]8 a· Excellent English and Mandarin skills
+ N" L  W) |$ }! d- M' m! b· Takes initiative and sets high goals, smart and confident
2 [& k4 }, `. k+ {" D. e· Self starter & ability to work in a team environment as an individual contributor
. G- X! L( ?: j2 L' K+ i0 N· Tracking record of planning and delivering successful verification projects
% f& y  D# E8 p' L, G· Expert of advanced verification methodology, like OVM, VMM
· Ability to test silicon using logic analyzers, oscilloscopes, and other common laboratory equipment is a plus.
· Thoroughly understand SOC development flow, solid knowledge of semiconductor technology
- L/ T) y0 m% A3 f0 W/ L1 w) z
Education & Work Experience:
# @) I- ?" \0 I( V· 6+ years of verification environment development & SOC verification
· 2+ years of team/project management experience;
· Expert in System Verilog and OVM or VMM verification methodology
· Proficiency in Perl, Tcl, Tk, C/C++, Verilog, System Verilog languages
· Master's Degree or above in EE/CE

Benefits:
# @* O5 z+ I) t, Z" J) K· Competitive salary
* M! P4 k% l% H" Z/ e· Stock options
· Excellent medical insurance plan
2 h! L# L$ {1 i· New product design bonus
- c* d  X$ R7 ]; {) G, l· Extensive training programs covering technology / management skills

ranica

招聘公司：A famous European IC company
招聘岗位：Senior Digital Design Engineer
- m7 }3 n$ }( J6 V9 Z, {( ]工作地点：Shanghai
2 S" R% p2 c: x4 P2 y8 w
0 D5 D% i5 l( m/ H, x6 ]岗位描述：
- Define specifications in cooperation with international teams - Design and verify digital circuits for mixed-signal application - FPGA-based verification of digital circuits - Estimation of efforts and schedules for design projects - Close cooperation and interaction with international teams
6 W4 ^' C% B" ^1 r
职位要求：
! w+ P2 [* |0 d3 g! ZRequirements: - Bachelor or master degree in Electronics, Communications, - Computer Engineering or equivalent, 2+ years - Strong background in digital design and verification - Experience in working with FPGAs - Flexibility and open-mindedness; Self motivated, excellent communication skills and a real team player - English written and verbal; - Willingness to work and interact in international teams

ranica

招聘公司：A famous IC company
/ s- e: D4 G4 D4 H- D' C2 w* _2 i- `招聘岗位：Senior / Staff ASIC DFT engineer (MCE ASIC)
工作地点：Shanghai
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" B& K9 O* X( ]+ I岗位描述：
Description: Sr. / Staff ASIC DFT design engineer Focus on DFT design & debugging of leading-edge large SoC.

' q$ N  b$ A  s$ e! n# r职位要求：
Qualifications: 1. BS (MS preferred) in microelectronics, electrical engineering or equivalent with 3+ years of DFT design experience, preferably with large SoC chips. 2. Handy experience on scan, mbist, boundary scan, ATPG and analog DFT, with Mentor/Synopsys/Syntest tools and RTL/gate simulation. 3. RTL design and STA experience is a strong plus. 4. ATE tester experience is a plus. 5. Must be able to communicate in both written and spoken English 6. Good team work spirit and communication skill.

ranica

招聘公司：A famous IC company
招聘岗位：Senior Digital IC Design Engineer (DFT)
工作地点：Shanghai
) ~5 ]8 n; w: c8 a, K. y( u, b5 L
7 S) Z4 z4 Z' `! L岗位描述：
Job Description: • Participate in SoC level DFT architecture definition • Implement DFT design for the SoC chips, cooperating with design team • Develop the high coverage and cost effective test patterns. • Generate and verify DFT patterns. • Evaluate and establish advanced DFT tools and flow. • Support other teams for DFT related problems

3 V% u. F' E$ e9 j9 u+ ?; u: C5 L: A! H职位要求：
6 O. ^6 I" N' QRequirements • B.Sc. degree or above in Semiconductor, Electronics Engineering areas • 2 year or above DFT or related design experience in industry • Good knowledge of IC design flow, including coding, simulation, verification, synthesis and STA. • Be skilled in the main EDA tools for design and simulation such as ncsim, RC/DC, Formality/LEC and PT. • Be familiar with Synopsys/Mentor DFT flow and tools • Proficient in Verilog/VHDL language. • Be familiar with shell/TCL/Perl grogram. • Good communication skill, will have frequent communication with foreign teams. • Good written and spoken English is mandatory

ranica

招聘公司：a top 15 semiconductor company
招聘岗位：Experienced Digital Designer
( m; O6 t1 i! m7 L工作地点：Beijing
! c: ?8 w, b6 C  z8 w* }- b
3 u4 u0 k. P7 y5 X岗位描述：
Responsibility: Participate in mix-signal IC development high speed mix signal products, working with multi-site engineers on different functions such as analog design, application, product evaluation and layout. The candidate is expected to contribute to signal chain understanding/partition, design, verification, synthesis, timing and power analysis. And he/she is also required be able to understand input from application engineers to translate real word issues to design requirements. Some basic lab skill to work with product evaluation engineers and understand real silicon issue is also desired.
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% m; T3 K2 H5 V9 G* w  f, s职位要求：
Requirement:  MSEE or PHD in EE related majors  4-10 years working experience on RTL related design, verification and physical implementation for FPGA or ASIC.  Be able to working with team mates to handel digital design from product concept to GDSII on each key task node, and have expereince on real silicon debug and probe.  The candidate should have basic idea on sampling theory and digital signal processing. Basic analog understanding with real mixed signal ASIC experience is preferred. High speed design experience is a good plus but not a must.  Self motivation, result oriented, good team work and communication skills.  Good spoken and written English  Supervision skill and project leader expereince is also required.

ranica

A famous IC company
0 }5 e) }. p3 `0 e. I1 i: e, N招聘岗位：Senior/Staff SoC Verification Engineer
工作地点：Beijing
; j- N0 l2 E/ f+ l; Z: H# X
; e, t9 S/ b0 o5 a& Z, a, b8 E: [岗位描述：

Responsibilities: Work with SoC architect (team) in design exploration and test cases definition. Build and maintain SoC chip level verification environment/testbench based on multiple IP level testbenches. Develop SoC level test cases based on architecture and functional specs and work closely with IP providers. Be responsible for a complete simulation coverage and verification closure at SoC level. Make the verification plan and commit to the time and quality objectives. Conduct RTL simulation and sign-off functional and timing simulation on back-annotated netlist. Work closely with the SoC architecture, IP design/verification, and validation teams in solving design and implementation problems. Strictly follow defined verification flow and rules. Report to IC dept. manager and project manager.

ranica

职位要求：
Requirements: Master or higher degree in Electrical Engineering or Computer Engineering. At least 5 years experience in IP/SoC function verification. Experience in portable device or wireless communication device IC design or verification is a plus. Solid verification skills and an expert in HDL language and using logic simulator e.g NCSIM. Hands on experience in verification language such as SystemVerilog or Specman E. Well understand OVM/UVM methodology. Experience in setting up SoC level verification environment is a must for senior position. Added value for those understanding SystemC. Hands on in UNIX environment and scripting language such as Perl and Tcl. Experience in verifying IPs of wireless communication or digital signal processing algorithm is a plus. Knowledge in IC/SoC architecture and design flow. Experience in FPGA prototyping or chip validation is a plus. Good English written skill. Good oral skill is a must for senior position. Ability in quick learning new knowledge and master new skills. Strong debugging and problem solving skills. Ability to handle multi-task at a time and work under tight schedule. Team player, willing to communication, proactive and self-motivated.

ranica

招聘公司：A fabless IC design company
招聘岗位：系统工程师(TCON)
工作地点：Beijing
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' Z, T/ g" {+ o4 {- m+ p/ Z岗位描述：
主要职责： 全面验证IC功能/指标，为客户提供系统应用的参考方案和相关文档，解决客户在实际应用中的技术问题，配合销售部完成销售目标。

7 I1 Z* U4 d6 ~  W职位要求：
职位需求： 1. 计算机、通信、电子工程类专业，本科及以上学历。英语CET-6级以上水平，良好的英文读写能力； 2. 熟悉LCD 基本知识及相应TCON, driver芯片相关知识，了解通信系统或民用消费类产品的框架结构及应用领域 3. 具备较强的芯片级理解能力，对高速视频接口（LVDS, DVI, HDMI, DP）、数字电视相关芯片有深入的研究或应用，可以很准确的知道芯片的指标含 义和解释； 4. 能够独立调试电源、CPU、FPGA及ASIC芯片，熟练掌握 Cadence或PowerPCB/Powerlog ic等软件，熟知原理图设计，PCB 的布线规则和产品的生产流程； 5. 具备敏锐和快速的反应能力；良好的思维能力、信息收集、分析能力； 6. 良好的团队合作意识和沟通能力； 7. 适应经常出差，勤奋刻苦，爱岗敬业。