When PCB layout area is not enough, we often use 4mil GND trace to shielding RF clock trace with 4mil spacing. 7 p9 k+ `; y h2 z3 c6 GIs this way enough to avoid RF clock signal to couple other signal trace near the 4mil trace? 7 t6 Y2 o) c# IThanks
u r proposed to refer to 3W rule. ; }5 ^# E4 b; ?9 T# P% ]& |
when clock trace is 5 mils, u will need 10 mils spacing.4 n& f1 B( ]( E( g5 ?' v) K3 \6 z
of course GND trace will help, but PTH through holes with proper interval will do it better.) w' H7 e' _, H' O6 W
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google it for detailed information, please!