When PCB layout area is not enough, we often use 4mil GND trace to shielding RF clock trace with 4mil spacing.. h {( J& m0 p4 y
Is this way enough to avoid RF clock signal to couple other signal trace near the 4mil trace? f J1 |0 y' f$ n- N3 v* v+ _6 [' G
Thanks
u r proposed to refer to 3W rule. / R' [: ~* J0 e# e0 c2 l. `5 \- Swhen clock trace is 5 mils, u will need 10 mils spacing.$ C K4 h, M# }( t8 q
of course GND trace will help, but PTH through holes with proper interval will do it better. 9 j2 ]* R; B8 s# l5 Y7 u# D 8 d1 W) e4 n/ Q: ?& K$ Kgoogle it for detailed information, please!