When PCB layout area is not enough, we often use 4mil GND trace to shielding RF clock trace with 4mil spacing.% I, G R# Z* C& P! J" @0 B
Is this way enough to avoid RF clock signal to couple other signal trace near the 4mil trace? " c. Z9 d2 G& v5 }5 B' m/ ?% Y' aThanks
u r proposed to refer to 3W rule. 3 }) }: V* ~" d/ E8 b1 H
when clock trace is 5 mils, u will need 10 mils spacing.5 j+ c9 t! f' R1 z% s J
of course GND trace will help, but PTH through holes with proper interval will do it better., ?, i2 w( a9 g
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google it for detailed information, please!