When PCB layout area is not enough, we often use 4mil GND trace to shielding RF clock trace with 4mil spacing. % U4 |' |4 P' x, T8 W, e1 l% QIs this way enough to avoid RF clock signal to couple other signal trace near the 4mil trace? O1 M3 y0 o& W$ m. V
Thanks
u r proposed to refer to 3W rule. 4 e7 R$ \. g( |8 {+ s2 ?0 x. L
when clock trace is 5 mils, u will need 10 mils spacing.0 }% ]8 `$ }# L% E& B. Q! z
of course GND trace will help, but PTH through holes with proper interval will do it better. ' N4 n5 i5 _* p: d/ D2 k+ ~9 [/ i
google it for detailed information, please!