When PCB layout area is not enough, we often use 4mil GND trace to shielding RF clock trace with 4mil spacing.$ A* h3 E$ @0 j
Is this way enough to avoid RF clock signal to couple other signal trace near the 4mil trace? X2 \4 W5 x. {- K0 e" [, \
Thanks
u r proposed to refer to 3W rule. 4 [, ^, P9 b) {% r- b0 kwhen clock trace is 5 mils, u will need 10 mils spacing.: L1 _' n4 n( m l, {
of course GND trace will help, but PTH through holes with proper interval will do it better. % T0 q: `4 Y( M9 [+ ^4 _1 Q6 f9 p3 p. p" |
google it for detailed information, please!