5/13 Open Verification Methodology (OVM)-System Verilog Workshop

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			活動類型: Workshop 活動日期: 13 May 2011 - 13 May 2011 9:00 AM 活動地點: Cadence益華電腦 我要報名 »

/ q! I( U) L' {! F# T6 u" K" [& YThe Open Verification Methodology (OVM) is the first truly open, interoperable, and proven verification methodology. The OVM is an open-source SystemVerilog class library and methodology that defines a framework for reusable verification IP (VIP) and tests. It is 100% IEEE 1800 SystemVerilog and provides building blocks (objects) and a common set of verification-related utilities. The OVM release will be under the Apache 2.0 license, enabling anyone to use OVM libraries for any purpose, including creation of derivative work.

-09:00-10:00: Coverage Driven Verification
7 \: v  a8 Z/ v! a: e: X-10:00-11:00: Stimulus Generation
0 K3 V% k( g4 ~; W$ \–11:00-12:00: Building Reusable Verification Components
, T2 o) S& b" h/ d–13: p00-14:00: Testbench Creation Using Reusable Components
! L9 k) D! I/ I9 q* ]–14:00-15:00: Coverage analysis and regression
–15:00: Summary