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實驗平台~$ o- [( f5 q$ z7 w
「Terasic」Altera DE0 多媒體開發平台,Cyclone III 3C16 FPGA! V0 C" t( n( a7 j) K0 j
在建構的過程中(僅放入cpu跟memory ip)
9 l7 q, a5 s2 a9 n/ `: o3 Vno reset vector has been specified for this CPU( F9 o/ A v# D
no exception vector has been specified for this CPU
/ a. i+ b9 S) K$ u這兩個訊息,沒辦法完全消除,這兩個一定要消除嗎
8 _6 s. d" w2 D% C3 f試過! X+ @* J0 \/ W2 Z, s1 z* I
on chip memory8 G" A0 h) A$ C- Y9 H/ u
sdram+ Y$ T4 j$ W! J6 r' [0 D9 M" ~
用上面兩個去試過所有可能的組合(mem/mem,sd/sd,sd/mem,mem/sd)
! P1 F& Y3 y$ c! y S( Y$ N4 a8 {no reset vector has been specified for this CPU! Q# u/ z9 S- [
no exception vector has been specified for this CPU. E8 P9 a1 H2 t5 r0 u) y5 ]0 E
總是會有一個沒辦法去除(先選的訊息會被消除)4 z: D8 z0 n5 J5 _/ n, A* j# B7 J
% W O9 z+ z% d有人有在玩10.1版嗎?請多多幫忙~~4 Z4 v9 O K- e
9 M0 w2 e% l {) g! n目前打算~改用10.0sp1跟9.1sp2試試看# d o) C3 r: m6 |
6 V$ N/ x+ |% s- Y, u( m G5 l$ mTHX~ |
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