Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits

semico_ljj

Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits
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semico_ljj

Abstract -- The diode operated in forward-biased condition has
# t! r& W+ x2 ?3 n) L5 {8 z0 _been widely used as an effective on-chip ESD protection device at
GHz RF and high-speed I/O pads due to the small parasitic
loading effect and high ESD robustness in CMOS integrated
2 _/ u# d. T+ X- s1 zcircuits (ICs). This work presents new ESD protection diodes
realized in the octagon, waffle-hollow, and octagon-hollow layout
styles to improve the efficiency of ESD current distribution and
to reduce the parasitic capacitance. The new ESD protection
diodes can achieve smaller parasitic capacitance under the same
$ D1 L* @! I- a* `: v; tESD robustness level as compared to the waffle diode. Therefore,
the signal degradation of GHz RF and high-speed transmission
can be reduced due to smaller parasitic capacitance from the new
proposed diodes.