Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits

semico_ljj

Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits
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sslin

謝謝大大的分享~~知識因分享而壯大！

+ C6 w1 Z! e0 S# g7 ]' f9 k- p# k~只有站在巨人的肩膀上才不會被食人族吃了!

zhifj86

thank you very much for your sharing

oscargo

正為ESD耐受度傷腦筋----

linger809

Abstract -- The diode operated in forward-biased condition has
been widely used as an effective on-c ...
semico_ljj 發表於 2010-6-25 08:50 AM

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不知道这种形式的ＩＯ有没有经过测试，实际的效果和预想的有多少的差别，thanks!

oika_51

看起來有幫助
感謝分享

caesarxl

谢谢楼主分享，非常感谢

linyuejing

下載來看看
下載來看看
下載來看看
, Y0 W( h) z  J+ f0 u! F下載來看看
% V  A; ?: c( A7 w9 ^! h% r應該有幫助
謝謝囉

xp212125o

看起來有幫助
感謝分享
; F4 Z5 D' J% f3 I6 N先下載來看看
$ B; d- ]2 Q3 Z( W0 i9 l( J2 ^' Pthank you ~

semico_ljj

Abstract -- The diode operated in forward-biased condition has
been widely used as an effective on-chip ESD protection device at
2 j! [; h8 N+ m8 R* DGHz RF and high-speed I/O pads due to the small parasitic
& O" z* Z$ `( {' {& p+ Qloading effect and high ESD robustness in CMOS integrated
circuits (ICs). This work presents new ESD protection diodes
realized in the octagon, waffle-hollow, and octagon-hollow layout
4 b  Y) D' F% T, p7 H! estyles to improve the efficiency of ESD current distribution and
2 U5 p! f) v0 s( ^7 Uto reduce the parasitic capacitance. The new ESD protection
5 m' v; r! n9 h8 ]. v  f+ Tdiodes can achieve smaller parasitic capacitance under the same
ESD robustness level as compared to the waffle diode. Therefore,
the signal degradation of GHz RF and high-speed transmission
can be reduced due to smaller parasitic capacitance from the new
- o. T- L4 Z' A5 U! O4 Dproposed diodes.