Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits

semico_ljj

Layout Optimization on ESD Diodes for Giga-Hz RF and High-Speed I/O Circuits

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sslin

謝謝大大的分享~~知識因分享而壯大！
' H. l! o. N) _- @
~只有站在巨人的肩膀上才不會被食人族吃了!

zhifj86

thank you very much for your sharing

oscargo

正為ESD耐受度傷腦筋----

linger809

Abstract -- The diode operated in forward-biased condition has
been widely used as an effective on-c ...
semico_ljj 發表於 2010-6-25 08:50 AM

% e, u/ Q$ J$ C7 O8 ]4 ?/ K8 e

不知道这种形式的ＩＯ有没有经过测试，实际的效果和预想的有多少的差别，thanks!

oika_51

看起來有幫助
0 C! P) h: y% E0 W感謝分享

caesarxl

谢谢楼主分享，非常感谢

linyuejing

下載來看看
下載來看看
4 {0 t4 L1 ]/ D, J( B下載來看看
下載來看看
' Z- g! Y. M/ [* q6 P9 q應該有幫助
( p3 ^2 h* |0 L+ r7 {% d( D謝謝囉

xp212125o

看起來有幫助
感謝分享
先下載來看看
& X  a  v, z' t! M" g- vthank you ~

semico_ljj

Abstract -- The diode operated in forward-biased condition has
been widely used as an effective on-chip ESD protection device at
GHz RF and high-speed I/O pads due to the small parasitic
loading effect and high ESD robustness in CMOS integrated
circuits (ICs). This work presents new ESD protection diodes
realized in the octagon, waffle-hollow, and octagon-hollow layout
styles to improve the efficiency of ESD current distribution and
to reduce the parasitic capacitance. The new ESD protection
diodes can achieve smaller parasitic capacitance under the same
ESD robustness level as compared to the waffle diode. Therefore,
the signal degradation of GHz RF and high-speed transmission
5 d- P& F; O9 o& U  Q0 scan be reduced due to smaller parasitic capacitance from the new
proposed diodes.