[關於] [jianping ]如何用verilog將變數前後補上幾個位元

tommywgt

因為無法回覆, 所以開新文回答....
1 s1 w/ L  W# V; l  lABT={2'b00, DATA, 4'b0000};

! q! Z$ T( D9 M# UVerilog 常用的operator
– Binary bit-wise operators: ~, &, |, ^, ~^, ^~
– Unary reduction operators: &, ~&, |, ~|, ^, ~^, ^~
– Logical operators: !, &&, ||
& i% ~: s) `/ [/ V– 2’s complement operators: +, -, *, /, %
; Y2 Z/ A* Q. l3 y) l5 _– Relational operators: >, <, >=, <=, ==, !=, ===, !==
1 ^8 A+ ]) ^) L+ d7 J1 n( V/ A( e" B3 G– Logical shift operators: >>, <<
: j3 U& ?4 b2 i! a0 ?9 w9 w– Conditional operators: ? :
) p; X/ T, |, a0 M1 m: ?  x– Duplication operators: {n{ <exp> <,<exp>> *}}
5 c3 U. q# e# @, |( y  c7 n' G– Concatenation operators: {}
給你參考一下