Chip123 科技應用創新平台

 找回密碼
 申請會員

QQ登錄

只需一步,快速開始

Login

用FB帳號登入

搜索
1 2 3 4
查看: 6581|回復: 6
打印 上一主題 下一主題

[問題求助] 使用暫態分析模擬出phasenoise @ MMSIM701

[複製鏈接]
跳轉到指定樓層
1#
發表於 2009-8-27 02:01:53 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
原文連結
3 x  d7 o/ ^6 Y; a
, h1 k( b" ~! P. ^9 h! T  `4 ^- c1 J以下原文內容:, G9 |+ e* M) x% }: V1 v
3 S2 v, P2 q+ k# c9 Q
Calculating Large Signal Phase Noise Using Transient Noise Analysis* E( `. x4 K" t9 [, n& F
By Alan Whittaker on March 26, 20095 i) Z3 Q6 r; d' Z
0 u: w4 g# U( M# T1 K/ [8 E
My name is Alan Whittaker and I'm in Cadence's Custom IC Proliferation Group.    x6 [* W& c4 T! d1 x
We support Cadence's Technical Field Organization (the AEs) and Cadence customers % E7 I: e5 Y3 H; L! p
during the introduction and adoption of new and advanced EDA technologies.  I'll
+ J/ i# f. V. O  ]) x, t: z7 J5 h2 Cbe posting here from time to time on methodologies and tool features that " B9 M* j3 |. ]$ B0 W7 ]
resolve issues that users have run into during the front-end analog, RF and * }, }- Q! h! b! K. K+ y1 ]( Y3 z
mixed-signal design process.
" v9 z/ Y* [/ {1 ?4 C0 v0 C4 `' E5 x
I'm first going to address how you can perform a large-signal phase noise 1 x9 ~- L" ^% U$ y) D' `
analysis on a design block such as a VCO using our transient noise analysis 0 V6 a8 p: @  ^/ L. u+ }
capability in our Spectre circuit simulator.  This approach is in addition to ; O* s" a- P* O6 j/ Y* a
our small signal phase noise analysis which is available using either pnoise
0 w( K4 Q7 l4 W: I4 {+ M' H4 Oor hbnoise analysis in the SpectreRF option to Spectre.) J. _* D7 j' _* i

# c. }! e) d: ^- [' xHere are the steps to obtain a phase noise plot from transient noise analysis:3 v$ s( s, X" M% }9 d0 }3 a

) ~& K& ~- A9 h% ^  d- o. r1.  Set up your oscillator testbench circuit for a transient noise analysis % D$ T) z% H; n2 w7 M' T$ S
(See sourcelink for the Transient Noise appNote - it doesn't discuss the phase
! E& r" s+ Z8 L+ P. M% fnoise measurement, but describes how to properly set up the simulation analysis
$ ~0 e6 I  z. N* @7 a4 B3 v$ I5 T0 ?& f
2.  Add the block freq_meter from the pllMMLib library
3 q4 ^) }; U* Q. a($CDSHOME/tools//dfII/samples/artist/pllMMLib) . K- K, W- P) g4 X+ ]4 A
to the testbench circuit. Important: The instance name for this block must be
0 e( i, y8 q  P/ s2 z+ F'vco_freq'.; c( q& y+ J1 ~; n% S
( o* o7 K; j7 v! j
If the oscillator output is differential, connect it to the vin_p and vin_n & M4 J" h/ h% d3 ]" w# N
pins on the freq_meter block. If the oscillator output is single ended, connect * @# `6 m1 M3 M3 D$ C7 l0 h
it to the vin_p pin and connect the vin_n pin to ground. Connect a noConn cell
$ H6 b4 U% b/ S1 d! gfrom the basic library to the out_freq pin.
分享到:  QQ好友和群QQ好友和群 QQ空間QQ空間 騰訊微博騰訊微博 騰訊朋友騰訊朋友
收藏收藏 分享分享 頂 踩 分享分享
2#
 樓主| 發表於 2009-8-27 02:07:34 | 只看該作者
The parameters for this block are (set Tools Filter to veriloga in the CDF " T4 D/ |" t; j
parameter form:% V" s) g" L! h) R. o
    *
, u" C' u. E2 D- A      Vthup: Threshold voltage to determine the rise edge of the input waveform. 7 f* n5 k/ }  |* Q) l
The input waveform period is determined by two adjacent rise edges. Default is 0. / X  W. j4 r# J+ d3 U
    *
: R8 e, S! g% O3 d, C      ttol: The tolerance of the time where the rise edge is determined. Default
8 |# S2 s3 o9 v2 m7 G% cis 1p.
, E# N. U4 a4 `) C* a    *4 {+ f% \# d( F
      outStart: The time-dependent period of the input waveform is output to the
+ z/ g  q4 c; ?# B6 Hfile when the time is greater than outStart. Default is 0. To get accurate phase 1 {8 ~7 k2 ], ?. b2 {. K
noise measurements, set this to past the time when the oscillator is fully
) {* T' S8 o% Zpowered up and oscillating at the design frequency.
/ f5 e0 j* ^* l% ~2 C* O    *8 D0 C8 g  K1 C  s# W; D
      outfile: The name of a file to contain time-dependent periods for use in 8 U1 S. z+ i! U; x4 W) R
later psd calculations. Specify just the file name, not a path. If outfile is
' P) g  f; V4 G! ^/ ?: Aleft blank, the default name is periods.txt.
3#
 樓主| 發表於 2009-8-27 02:11:04 | 只看該作者
3.  Before starting the simulation, in the ADE window, Select Tools->RF->LL. In the PLL Macro Model Wizard window, enable PLL Macro Model and select PLL Bench as the Bench Type. Then OK this form.* v, _8 ]# J7 t2 z$ C: @% W
3 i( l( E1 |. {- u
4.  Run the simulation. The simulation must run successfully to completion in order to get to the phase noise results.# L5 j. u& K- n0 a3 i' D& ^

8 w. I$ l; z) x/ z5.  In the Direct Plot form for transient noise there should be a PLL PSD Noise option. This will allow you to plot the phase noise results. If a message appears saying that the PLL Noise PSD data is not available, check steps 3) and 4). If you make any corrections, you will need to re-run the simulation.% a, Q: M( O  F  d8 z  p
7 o$ _+ j' Q5 T$ b% E2 X9 V8 n
The phase noise plot will extend from fmin = 4/tstop to fmax = fosc/2, where tstop is the transient noise simulation stop time and fosc is the oscillation frequency of the circuit.
7 \3 {2 L# E* w& ?& R6 c2 V5 O) B% A- k- _
Important note: You will need to use MMSIM701 and IC5141USR5 or IC613 (or latersubversions) to obtain a phase noise plot from transient noise analysis.
2 I  y2 @7 T5 |, S* @
8 v; z3 s# b2 N' U0 T; i我用的是mmsim620,也不能模。有人可以模擬出來的回個文,show個圖給大家看吧
4#
發表於 2009-9-24 17:41:38 | 只看該作者
show you my simulation result( {  C( D+ l( W4 i
!!!6 G, d4 _3 D  D9 A
!!!!!!!!!!!& p8 |' l" y+ I, M9 D  O/ _& {
!!!!!!

本帖子中包含更多資源

您需要 登錄 才可以下載或查看,沒有帳號?申請會員

x
5#
 樓主| 發表於 2009-9-25 16:46:23 | 只看該作者
謝謝你的回覆,我最近拿到新的軟體也開始在測試mmsim7了
  {7 U+ [$ |! K" s0 b2 p7 L/ c我發現turbo與multi thread的設定不同會對結果造成很大的不同。* S, h0 l* L! P2 y' N8 N
還有這個phase noise的訊號的範圍跟transient noise的設定與transient 的設定都有很緊密的關係。0 Q9 D$ A3 ]; w* F$ y, ^4 q) E
不知道該怎麼作設定才是比較準確的
6#
發表於 2011-5-6 00:39:50 | 只看該作者
請問有更詳盡的使用方法嗎
7#
發表於 2011-5-26 15:02:19 | 只看該作者
也去试试这个流程。关于pll相噪仿真还有其他方法吗?
您需要登錄後才可以回帖 登錄 | 申請會員

本版積分規則

首頁|手機版|Chip123 科技應用創新平台 |新契機國際商機整合股份有限公司

GMT+8, 2024-4-29 07:49 AM , Processed in 0.115007 second(s), 19 queries .

Powered by Discuz! X3.2

© 2001-2013 Comsenz Inc.

快速回復 返回頂部 返回列表