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[經驗交流] 請教90/65奈米,SOC Tape-out一次NRE大約多少

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1#
發表於 2009-8-13 10:26:46 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
如題" r# y! h9 m. V1 A9 |

: X. {& T- D; u& N9 {# v請教業界各位先進
; I4 ~  U( @- T) ~% a" i0 m% E% \" L目前的chip開發,需要多少投資?! y2 u/ h$ m6 F4 e) L* G% }5 H
首先是假設 Febless design house.- b6 c% I6 B3 [; U
自家由algorithm 到 RTL simulation 完成
+ z: ~4 F5 E7 l! ?5 c後端包給 backend service 公司 (layout, mask, Fab, assembly..)! m+ c! b( L! p1 G7 G* [" Z3 F
以 ARM9 or ARM11, AMBA2.0 為platform5 ?# W+ f- I& N/ b
那麼2 E- \$ T4 j9 J! i8 w. F4 t
  (1)90奈米, NRE大概多少?( v; j  o" I5 s) b, q! u
  (2)65奈米, NRE大概多少?
! N/ a1 A8 m' ^& u- g) w8 L$ l  (3)或是您知道其他製程, NRE大約多少...$ j0 x/ A2 L% z# x! H6 b2 M

! e$ Y2 d  B) M* a& j  y2 Q. O& G謝謝
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2#
發表於 2009-8-14 01:17:51 | 只看該作者
Which design service company you will go to?/ G7 y  o7 S) h: x
How many mask layers it will be?
. @% G$ y' e" aBesides, ARM, any other IP, like DLL / PLL / EDRAM / USB / LVDS..... and who will be the IP provider(s), wafer Fab? design service companies? or 3rd parties?- f7 I/ l0 D% i
How many chips you need? A full set mask or MPW?7 x7 b8 r# e- I- H: g2 }; Y0 f
What package you need?
3#
 樓主| 發表於 2009-8-14 08:59:04 | 只看該作者
Well,) S2 B' b' b; d4 e+ ~
4 ]: U- v; C) }
I just estimate the investiment of a ASIC team.
% `7 k& k' L. o% _/ dnot servey for a project.: W1 U8 \# f' q- F' q" G
So, I just want to know the range of NRE.  }4 p! b) q: @1 V( J/ l( u$ l
' B, H3 [/ [. b4 h
For example, It will be
8 O2 e) V7 L* E5 E% g' C(1) 5,000,000 NT$ ?
& s; N6 i7 t! Q. P6 h(2) 8,000,000 NT$ ?  `+ p4 a, w) n, _& T! s  R6 o; `
(3)10,000,000 NT$ ?8 B7 ~' {5 M; `' i( K
(4)12,000,000 NT$ ?) V* O- M7 i% d# d- l9 x' v
(5)15,000,000 NT$ ?5 u* s- y/ d2 L8 m8 k
% Q7 ^! S6 j1 X+ z& C# @
Sure, I understand following things:
# C* B' x1 J6 v6 }& D4 P2 q$ D - full set mask cost more$ G. Q3 Y6 s+ U) y
- PLL/LVDS... analog IP are extra cost5 B0 L" l' U$ M1 c7 }8 o
- pin-count and area also influence cost
  I2 P% Z) |) S/ i0 q+ H - different package also cost different
- Y1 R: f6 \) ^) n# a7 W% a3 I# x9 _# C5 i
Therefore, if really need information for estimate,3 Y! I" X$ X( B$ H
just for example.
7 X1 i$ Z- ~- W7 t, ULet's assume a SoC for FullHD TV application
- s3 Q# u# `9 v3 n3 G) S; uit will include
' ^" t1 |7 g9 ]- R/ M# e1 c  - ARM AMBA
# @# I- Y2 k5 D$ F) _% e  - DDR2 I/F9 x! f8 d  ]) f. P( ?, p
  - GPIO, IIC,.... G8 {% C7 L* J
  - LVDS out (dual link)
! ~7 p, ?* \) u6 A7 J6 l3 @  - Video-in: HDMI(1.2)x2, VGA, YCbCr, A/V, S-V, SCART,
9 O( K2 f8 N1 g! n5 l  - 12bit ADC, 10bot ADC x2
7 ]8 \) u/ S  L9 D5 b3 W- I3 x  - PLL/DLL
& X% H# [" S/ e' ?% z8 Q& g5 L  - 256 pins 以上
, n, D* P: m. z+ F" W: O! x8 T
3 w. B9 u+ t4 Q- l9 g* f7 }, e6 nThan,... any idea about NRE fee?. d0 H: D) |! k2 m: O) q6 S
again, I just want to know the range
4#
發表於 2009-8-14 09:25:01 | 只看該作者
if the ARM and AMBA is hardcore,
3 J$ g- W2 @1 Bbasically 65nm-->USD$1M above and 90nm-->700K above) S1 R3 Q9 h3 ?; N, a% B
and base on different foundry has difference price!. g9 C6 L& x: M% }3 D1 u
this price did not include any specific IP like TV encoder, decoder, vedio codec....- E1 z/ b: @% Z5 D  [
and did not include the ARM licensee...  s- ?8 v# K& ?5 H0 o( H! k
actually! it is not so much IC design in Taiwan tape out 65nm till now!
5#
發表於 2009-8-14 09:28:45 | 只看該作者
sorry, this price also did not include the shuttle or pilot run wafer(basically in 65nm will be USD$3xxx at 13pcs wafer)5 f6 z! E$ m& J' y' i8 ^
and package&testing, so you may count it at USD$1.3~1.5M if you are running turnkey solution!
6#
發表於 2009-10-22 11:06:45 | 只看該作者
need 1M dollar?
7#
發表於 2009-12-15 21:05:38 | 只看該作者

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