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[經驗交流] 請教90/65奈米,SOC Tape-out一次NRE大約多少

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1#
發表於 2009-8-13 10:26:46 | 只看該作者 回帖獎勵 |倒序瀏覽 |閱讀模式
如題9 H% {3 X% J, q
. h) r1 \" A- I
請教業界各位先進
5 A$ T- A" L, B  j* J( ]. t' i5 ~. w目前的chip開發,需要多少投資?
- U8 D. M& W+ Q. R" \5 L首先是假設 Febless design house.7 N* _' n6 C1 n& H' s/ k0 L
自家由algorithm 到 RTL simulation 完成% b9 o  k3 D& ~6 A4 S; K/ G
後端包給 backend service 公司 (layout, mask, Fab, assembly..)% t5 I5 s  U' d& i* W! W, U4 Z
以 ARM9 or ARM11, AMBA2.0 為platform
' c1 l$ B4 M; x" {那麼( k* ?! w, O* H3 \
  (1)90奈米, NRE大概多少?
) L" j8 H7 ?  P- l# `6 T2 j; ?7 A* w  L  (2)65奈米, NRE大概多少?* R7 ]( K; a  B! m; G
  (3)或是您知道其他製程, NRE大約多少...# v; G2 |7 \7 Y% l- U
0 r; I( M6 |+ G" @9 ?3 j" {
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2#
發表於 2009-8-14 01:17:51 | 只看該作者
Which design service company you will go to?
+ D. ]& d( y$ U8 `; q7 `) DHow many mask layers it will be?
) k/ q9 R; m. H+ l. iBesides, ARM, any other IP, like DLL / PLL / EDRAM / USB / LVDS..... and who will be the IP provider(s), wafer Fab? design service companies? or 3rd parties?3 U0 p% q9 w; Q4 u
How many chips you need? A full set mask or MPW?
/ k, q3 S) T1 z/ p' }What package you need?
3#
 樓主| 發表於 2009-8-14 08:59:04 | 只看該作者
Well,
' k; w% @, I2 u# |8 H1 M
- [5 y. E1 `6 j0 {- @I just estimate the investiment of a ASIC team.
* R. a& \6 M0 `! g& d/ F* V2 Qnot servey for a project.8 B/ N# d8 h" J: u# F
So, I just want to know the range of NRE.
! {. ?$ |- a5 e) w  v; T. \8 i5 d
For example, It will be 5 e; x0 J" k) F( e  c
(1) 5,000,000 NT$ ?
' R2 n( D- U: i4 w! I. R$ X(2) 8,000,000 NT$ ?1 Q$ s6 u  C( O, R' K- n
(3)10,000,000 NT$ ?
4 p' G" y* c4 n0 z(4)12,000,000 NT$ ?9 |! S# q% {  D+ F! S
(5)15,000,000 NT$ ?+ s4 a- q- K! h
( P0 d. ^# e- B+ w2 o
Sure, I understand following things:
$ u! {3 D6 H& J2 v# M - full set mask cost more
; A7 Y9 }" i5 ~% }( j - PLL/LVDS... analog IP are extra cost
" @4 x# u4 C7 p# ~$ z - pin-count and area also influence cost3 K6 w% q0 u1 o3 N7 H8 |+ t
- different package also cost different
2 [3 t; \/ O' l6 p4 s% A$ {/ e" X+ n" {8 T) U5 g8 ~# r, @  Q
Therefore, if really need information for estimate,2 p5 P# Y5 Q% o+ z  [$ r& y4 o" |
just for example.
- d6 p& E& ^3 B( j6 @3 X1 lLet's assume a SoC for FullHD TV application9 R8 [8 F% I, h9 e9 q
it will include; g! y& f1 @7 u2 v' {3 n- G# s
  - ARM AMBA
: X( _& a! [/ n6 v5 G/ ]6 f  - DDR2 I/F
' u$ U% ]+ S2 l* S" [1 z9 r- b8 L  - GPIO, IIC,..." x4 S3 R7 s8 F! N/ V8 v6 [" H
  - LVDS out (dual link)
& K" P* b# o& U; ?2 t1 L  - Video-in: HDMI(1.2)x2, VGA, YCbCr, A/V, S-V, SCART,) ^4 p0 m9 q; K
  - 12bit ADC, 10bot ADC x2
; U6 _% J( g( X  p  W- b  - PLL/DLL
/ z# H/ A+ C+ S, x$ V  - 256 pins 以上+ _' e3 O8 D9 S2 l$ i- R

6 M6 ^9 M6 U' CThan,... any idea about NRE fee?3 h! ~; C9 @1 T( R) R
again, I just want to know the range
4#
發表於 2009-8-14 09:25:01 | 只看該作者
if the ARM and AMBA is hardcore,
; u* n. \. U2 p* ]7 e3 Xbasically 65nm-->USD$1M above and 90nm-->700K above
* ]: ], u. k% j: T2 w4 gand base on different foundry has difference price!
; }- _: e; z- k9 Othis price did not include any specific IP like TV encoder, decoder, vedio codec....
  k! e7 j& W! j- `$ M7 `and did not include the ARM licensee...2 x" V. D5 y$ c2 W3 y% y9 q
actually! it is not so much IC design in Taiwan tape out 65nm till now!
5#
發表於 2009-8-14 09:28:45 | 只看該作者
sorry, this price also did not include the shuttle or pilot run wafer(basically in 65nm will be USD$3xxx at 13pcs wafer)
( }5 U/ K$ V$ E. a. mand package&testing, so you may count it at USD$1.3~1.5M if you are running turnkey solution!
6#
發表於 2009-10-22 11:06:45 | 只看該作者
need 1M dollar?
7#
發表於 2009-12-15 21:05:38 | 只看該作者

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