Bit rate and protocol independent clock and data recovery 6 O- O' c4 l" C% }; ^: z; P" m9 t* J! z) l
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Abstract' m+ c) m0 k7 S( Z7 d2 x1 x( x
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A design for a bit rate and protocol independent clock and data recovery circuit (CDRC) for use : P+ x5 l7 l& a) e: f9 U' @8 ?& E( s/ T! h. J+ d8 y$ Y
in optoelectronic regenerators is presented. A conventional phase-locked loop (PLL) has been : y; A" E6 S2 \" Q6 N# k; ] _' C' w8 ~+ }; @extended to a combined phase/frequency-locked loop by adding two additional frequency detectors (FDs). 2 `+ v6 _ D* Y# @% K2 g0 i& L/ F( `" ]3 H/ D0 n
This architecture guarantees reliable clock synchronisation of the input data with different line 0 U9 D8 M; H) N7 C9 W+ j) h1 |
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codes over a frequency range spanning multiple octaves $ e7 E6 K3 T/ I8 m( I/ a8 d5 z- N4 h) E4 h2 B1 d2 u( p$ n7 r
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