Bit rate and protocol independent clock and data recovery4 Y+ Q# }4 m4 G8 i4 M
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Abstract! L8 o/ K: g9 M
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A design for a bit rate and protocol independent clock and data recovery circuit (CDRC) for use 6 ^! b! }- b7 u 1 } {8 i' K* q5 ^+ Iin optoelectronic regenerators is presented. A conventional phase-locked loop (PLL) has been 9 r( f! i/ D5 m! T3 x( a - V2 f! X' r# k/ `( z5 Z3 xextended to a combined phase/frequency-locked loop by adding two additional frequency detectors (FDs). 5 ~: ^& z. b5 ]3 K
6 k& H# X: Y8 K1 BThis architecture guarantees reliable clock synchronisation of the input data with different line ; X: r# Q9 G9 b
* m8 K* z: X2 P1 w: r% T/ ^9 h$ O( Ycodes over a frequency range spanning multiple octaves& \" F6 r% o: O0 {
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