Layout Guidelines for Optimized ESD Protection Diodes

semico_ljj

Layout Guidelines for Optimized ESD Protection Diodes

Karan Bhatia and Elyse Rosenbaum
  r6 L* s9 U5 KDepartment of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign
- l) B, X9 w% K* \- G4 U4 n9 O: M1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu

- R$ b# s; P/ j( P6 a2 h6 h. MAbstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are
investigated. The current compression point (ICP) is introduced to define the maximum current handling
# C! @0 _% @; `3 e. e# T# {capability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the
& ~3 }' A# l$ ^* bperformance of the structures investigated herein.

semico_ljj

The dual-diode circuit has been found to be a suitable
ESD protection circuit for GHz-frequency CMOS
I/Os [1]. Layout-optimized ESD diodes provide a
5 w6 D6 B0 ?: b0 `high protection level per unit capacitance (C),
minimizing the performance degradation they induce
on high frequency I/O pins.

mousestack2003

感謝大大分享這些資料∼

讓我們了解led的一些事情∼

majorchen

權限不夠,真想看看layout guide要注意什麼...
真是可惜...

guillermo

感謝樓主的分享!小弟最近剛好遇到ESD的問題!

dike

真想看看  與工做相關
. e9 r" R! ^  B4 c小弟最近剛好正在研究ESD中  謝謝

allenearl

发现一个很好的网站,有很多EMC&ESD设计方面的资料,完全免费的.
www.gooemc.cn

hing

很棒的參考資料，謝謝分享！

yoyoseven

謝謝你的分享
1 ]6 d2 x! s& L" q現在急需esd的防護方式