Layout Guidelines for Optimized ESD Protection Diodes

semico_ljj

Layout Guidelines for Optimized ESD Protection Diodes

Karan Bhatia and Elyse Rosenbaum
Department of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign
1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu
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Abstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are
investigated. The current compression point (ICP) is introduced to define the maximum current handling
2 U  g8 }9 }- b! _$ n7 l8 ncapability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the
performance of the structures investigated herein.

semico_ljj

The dual-diode circuit has been found to be a suitable
' a/ i: d4 Z" A: D# G8 sESD protection circuit for GHz-frequency CMOS
6 d( C2 D6 b3 I/ @: s( aI/Os [1]. Layout-optimized ESD diodes provide a
% q3 P8 L1 l9 k/ P/ b. thigh protection level per unit capacitance (C),
6 F/ k" w* M1 j: ^8 V* }minimizing the performance degradation they induce
on high frequency I/O pins.

mousestack2003

感謝大大分享這些資料∼
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1 Z7 I3 \! a- l讓我們了解led的一些事情∼

majorchen

權限不夠,真想看看layout guide要注意什麼...
真是可惜...

guillermo

感謝樓主的分享!小弟最近剛好遇到ESD的問題!

dike

真想看看  與工做相關
小弟最近剛好正在研究ESD中  謝謝

allenearl

发现一个很好的网站,有很多EMC&ESD设计方面的资料,完全免费的.
www.gooemc.cn

hing

很棒的參考資料，謝謝分享！

yoyoseven

謝謝你的分享
, e, _. d8 d% [5 k8 w9 R現在急需esd的防護方式