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Layout Guidelines for Optimized ESD Protection Diodes: v3 N" x% W6 c5 b
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Karan Bhatia and Elyse Rosenbaum6 H$ M# b, o+ E: ?
Department of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign& V* e6 ^) _4 d! h2 L6 O9 g
1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu- A- o) ^! z# O! B( {
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Abstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are% M% N1 E; _6 |4 B: u* Q9 z
investigated. The current compression point (ICP) is introduced to define the maximum current handling( u0 p. C- m! D& l& s
capability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the. d. j2 N0 {5 y# w: a
performance of the structures investigated herein. |
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