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This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter
) t1 d/ E! u: y3 }+ N. aAttenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance& ^; Q$ u ?3 d$ L1 j0 ^
on par with commercially available PLLs, while being relatively simple to design and use as
' }4 w& y. u. v* z* M/ a! i+ p: qan on-chip solution. The main difference between the JAC and PLLs is that the JAC does8 w) w6 u6 e. `- `# e
not guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In L# ~) S# U9 a
the following sections the effects of jitter, present methods to reduce jitter, and application* I# T6 v6 m- t+ Q
of the JAC will be discussed.
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