Berkeley的一篇博士论文_Jitter Reduction on High-Speed Clock Signals

hitxiaojun

This thesis discusses an alternative jitter removal circuit dubbed here as the Jitter
% S: }: u% ^, b8 m. F' rAttenuation Circuit (JAC). The goal of this circuit is to provide jitter reduction performance
7 t& n+ C8 v$ s0 A5 T  Bon par with commercially available PLLs, while being relatively simple to design and use as
an on-chip solution. The main difference between the JAC and PLLs is that the JAC does
0 x5 G% x5 A$ k6 C: Tnot guarantee any phase alignment with its input. Its sole purpose is to remove jitter. In
the following sections the effects of jitter, present methods to reduce jitter, and application
! U4 U1 a% x/ @of the JAC will be discussed.
8 Y- E( ~  w9 \$ u5 q* R8 i
6 m  I8 R1 v# y

遊客，如果您要查看本帖隱藏內容請回復

satto0216

謝謝大大…dll&pll的任何相關資料我都很需要
* [9 C. G# M( n* g4 {) E) @6 w希望可以幫到我，

liyao

剛好工作上碰到jitter measurement問題,下載參閱一下,感恩!!

liyao

> < 我很少上來 沒錢下載 怎麼辦呀!!

anita66

Wow, 新的耶?!真是太讚了, 先下來study看看, 有機會在跟大家分享心得, 3Q~

planet1114

最近在工作上一直被noise所困擾,
下來看看能不能從這有新的啟發.
先謝啦

godman

謝謝你的分享，希望會有所幫助。

b56389

多看看別人所推薦的paper
7 N% T" t9 }1 L5 ], k9 T5 A5 G4 _研究其的看法與理論
相信對增進自己的實力有幫助的

donnie

Thanks for Sharing
" F0 `5 x: X8 nThanks for Sharing

donnie

Thanks for Sharing!
- r. P( ~+ t# eThanks for Sharing!

ychchip

jitter is important issues in analog ic design.  it must be carefully designed including path match and high speed.

eceking

可惜沒足夠的錢幣............................................................!

anita66

感謝大大無私分享, 不知道有沒有跟Thomas Lee的論點是否相同??3Q~

xp212125o

thank you~
感謝分享
正好有需要

lyx1982

谢谢分享！收藏了！！！

starfish311

回復 1# hitxiaojun


8 w# X" G' {5 n' l    謝謝你的分享，希望會有所幫助

ja1688888

剛好需要看PLL jitter 學習一下 感謝

alienwarejian

谢谢
谢谢

microuser

感謝大大無私分享，剛好需要看PLL jitter 學習一下 感謝

microuser

感謝大大無私分享，剛好需要看PLL jitter 學習一下 感謝！