請問由Verilog code到IC layout 需要哪些軟體

leesg

問題, 已完成 Verilog code 設計, 模擬(ModelSim)
想要用軟體直接 run 到 IC Layout 產生 die photo,
% V7 A; k' a5 r3 P# ?要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout)
1.
7 I9 _$ C% [/ y8 Cdesign compiler + Astro ?

2.
7 O# C- ~2 X3 h+ j$ t4 f% Usynopsys IC compiler ?

5 x; q; ^- S* G* t2 B4 ?7 D' t, w3.
cadnece virtuso ?

lee100

Synopsys R2G flow
1. rtl simulation by vcs
2. synthesis by design compiler ultra with dc/dct mode
3. dft insertion by dft compiler
4. jtag insertion by bsd compiler
5. ICG insertion by power compiler
6. pre/post-layout STA by prime time
7. pre/post-layout power analysis by prime time px
8. PnR by IC compiler
( o: |2 a0 Y) Y5 |) W, A. Y9. post-layout SI analysis by prime time si
% Q6 F2 [) K2 u" G, c7 O2 ?; h10. post-layout simulation by vcs

putechen

sometimes ,star-RCXT is necessary.just for layout PEX.

yytseng

after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.
clean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.

ejean

1. magma is another solution
/ Z7 M3 P9 F: j* R' \& [2. Astro  from synopsys
3 S* p# i; I4 j2 S( j3 Y: C3. FirstEncounter from Cadence

All with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.

ilovepachaya

私心推薦APR使用IC Compiler  效果很好