請問由Verilog code到IC layout 需要哪些軟體

leesg

問題, 已完成 Verilog code 設計, 模擬(ModelSim)
想要用軟體直接 run 到 IC Layout 產生 die photo,
要用什麼軟體組合 ? (輸入 verilog code, 自動跑出 IC Layout)
$ r& J2 h! D, f. y* R4 J1 E! x1.
design compiler + Astro ?

4 @0 A8 }# _  O; D2.
synopsys IC compiler ?

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cadnece virtuso ?

lee100

Synopsys R2G flow
1. rtl simulation by vcs
& R. ?0 P3 @1 b: N: ?2. synthesis by design compiler ultra with dc/dct mode
3. dft insertion by dft compiler
" {" {4 J; v% _( J9 J8 e8 W" P4. jtag insertion by bsd compiler
/ Y0 @7 F( a( z0 l5. ICG insertion by power compiler
6. pre/post-layout STA by prime time
7. pre/post-layout power analysis by prime time px
4 _3 s2 e2 U- M$ t. F8. PnR by IC compiler
9. post-layout SI analysis by prime time si
7 g1 N: C# b8 R10. post-layout simulation by vcs

putechen

sometimes ,star-RCXT is necessary.just for layout PEX.

yytseng

after above place and route task, you need virtuoso or laker to merge cell layouts and do some editing.
& S1 {% K) t3 t$ p9 w. mclean up LVS/DRC/ERC/ESD violations with calibre or (hercules, assura) tools.

ejean

1. magma is another solution
2. Astro  from synopsys
+ o- y! ~. B8 V7 L; [3. FirstEncounter from Cadence

5 H& R( i4 S8 k" nAll with basic DRC and LVS, you have to run Calibre, etc. to finish the final verification.

ilovepachaya

私心推薦APR使用IC Compiler  效果很好