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Startpoint: U_RST/nResetUSB_reg
`9 k5 D4 x# C, X, k; P (falling edge-triggered flip-flop clocked by CLK48)
# X" V: `0 p" m4 ? Endpoint: u_FUSB/FUS/BIF/PS/q_reg_2_
& g% X7 J# b$ q7 [ g0 C' A (rising edge-triggered flip-flop clocked by CLK48)
7 Q; [/ q7 j V6 @ Path Group: CLK48
% K1 Q8 \6 H9 B Path Type: max
1 D! @6 N, q( W/ x6 q' E) A4 C
Point Incr Path7 c- ?2 O* ^; i2 Y2 O. I1 u* _& f
--------------------------------------------------------------------------% s" H5 J: U3 X6 u4 c, Y
clock CLK48 (fall edge) 9.00 9.00
9 w# K- o7 b `1 [$ F% v clock network delay (ideal) 2.00 11.004 v% k; l. t* |! G1 @2 e4 q
U_RST/nResetUSB_reg/CKB (DBFRBN) 0.00 11.00 f
, V! U3 w/ w" l5 y U_RST/nResetUSB_reg/Q (DBFRBN) 1.27 12.27 r
3 {; b5 j7 D6 A( Y; [) |% z U_RST/nResetUSB (ResetGen) 0.00 12.27 r! ?5 l G$ Z" v# b
u_FUSB/RESETN (kFUS100_2m) 0.00 12.27 r
; M% x: E& f4 E* K4 z/ T u_FUSB/U132/O (BUF1) 0.32 12.59 r
1 j L" c0 {) S% X) d9 j; w u_FUSB/FUS/RESET_INN (LFUS) 0.00 12.59 r7 \5 m& M: Q8 E1 ?! G5 d
u_FUSB/FUS/BIF/RESET_INN (LUSBIF) 0.00 12.59 r
; H2 r, @3 ]/ m" l1 {( f, ^ u_FUSB/FUS/BIF/U42/O (BUF1) 0.33 12.92 r
7 U! X/ ` a6 n, \$ _/ F u_FUSB/FUS/BIF/U49/O (AN2) 0.44 13.36 r$ R8 _' ]/ F/ z
u_FUSB/FUS/BIF/U50/O (AN2) 0.64 14.00 r/ P/ ^9 p/ ]# ~7 D
u_FUSB/FUS/BIF/RESETN (LUSBIF) 0.00 14.00 r
# g0 {) h. I% H- ^: p6 p6 { u_FUSB/FUS/U44/O (BUF1) 0.69 14.69 r0 j7 a' w# v0 M, m$ i) V
u_FUSB/FUS/LDSCR/RESETN (LDSCR) 0.00 14.69 r
( `4 H9 K% I3 f1 z% ] u_FUSB/FUS/LDSCR/U85/O (INV1) 0.22 14.91 f. X' a' G& o$ w
u_FUSB/FUS/LDSCR/U222/O (NR2) 0.46 15.37 r
" h0 }0 Y& u7 ~ u_FUSB/FUS/LDSCR/U8/O (AO12) 0.46 15.83 r
) I' f2 e7 \/ d* F u_FUSB/FUS/LDSCR/U10/O (AN3) 0.50 16.33 r2 b; J, Y- T) ~: t: q
u_FUSB/FUS/LDSCR/U7/O (AO222) 0.51 16.84 r$ H9 Y4 m E3 z; r; U% B9 t
u_FUSB/FUS/LDSCR/U206/O (AN2) 0.36 17.21 r1 v' [% {9 q( s) R$ E
u_FUSB/FUS/LDSCR/epC/InterruptRD (LDSC_EPC) 0.00 17.21 r
, V# ]0 |; K1 s& X; D+ ?" ` u_FUSB/FUS/LDSCR/epC/U87/O (INV1) 0.12 17.33 f
6 M: E: T8 V! D: Z8 n% { u_FUSB/FUS/LDSCR/epC/U83/O (OR3B2) 0.34 17.66 f
! M) y+ g2 f k u_FUSB/FUS/LDSCR/epC/U82/O (NR2) 0.38 18.04 r2 ]8 O0 @# k1 R# i
u_FUSB/FUS/LDSCR/epC/U63/O (AO112) 0.50 18.54 r6 p% ^' L- o M: @3 S3 r8 ?, s
u_FUSB/FUS/LDSCR/epC/D_epC[2] (LDSC_EPC) 0.00 18.54 r
0 V8 O) S t+ B9 m2 h0 r u_FUSB/FUS/LDSCR/U158/O (ND2) 0.12 18.66 f( j4 f& R+ `6 L4 z
u_FUSB/FUS/LDSCR/U156/O (OR3B2) 0.19 18.84 r) S& @1 I @0 i+ q* \
u_FUSB/FUS/LDSCR/DD[2] (LDSCR) 0.00 18.84 r, ^. Z" {" D* }2 O5 o
u_FUSB/FUS/MIS/DD[2] (LMISC) 0.00 18.84 r
3 T3 p, R4 ]8 G& M u_FUSB/FUS/MIS/U47/O (AO222) 0.36 19.21 r
$ A v3 e0 I. |8 G5 Y( x) R$ [ u_FUSB/FUS/MIS/U45/O (OR2) 0.26 19.47 r
& O7 B: Q, H# d3 G4 w: |3 E u_FUSB/FUS/MIS/Q[2] (LMISC) 0.00 19.47 r
5 J2 N% i( t: H: M6 R u_FUSB/FUS/BIF/DOUT[2] (LUSBIF) 0.00 19.47 r/ U. I4 F* f. C4 k0 ]) p
u_FUSB/FUS/BIF/U29/O (AO222) 0.32 19.79 r2 U# c ^- O% m, A6 i! P2 Q
u_FUSB/FUS/BIF/PS/DIN[2] (LP2S) 0.00 19.79 r9 `5 a' y) ^6 O+ t3 v
u_FUSB/FUS/BIF/PS/U6/O (AO222) 0.33 20.11 r+ M" ~/ Q; s; O/ @4 t4 O
u_FUSB/FUS/BIF/PS/q_reg_2_/D (QDFFN) 0.00 20.11 r
. O: e. r4 r1 Z C9 K data arrival time 20.11! M+ \# G. f5 m$ n- G h; X
7 ~/ G$ F2 }4 o% v) H& u F
clock CLK48 (rise edge) 18.00 18.00
' y* }. T2 S* H5 l clock network delay (ideal) 2.00 20.00! {( t' d8 g/ k& ^
clock uncertainty -0.50 19.50/ Q* t# s. _2 R+ D. d. R
u_FUSB/FUS/BIF/PS/q_reg_2_/CK (QDFFN) 0.00 19.50 r
1 E; N1 K2 }) e' W5 }8 w9 l, Q library setup time -0.25 19.258 E! m N* v; ?' I
data required time 19.25, q: }+ C0 F) w2 ~7 G/ r6 P7 M
--------------------------------------------------------------------------. E' E/ F. K/ T* @8 f$ g6 h
data required time 19.259 @3 O* v3 k6 r" ^
data arrival time -20.11
@" w. R/ R$ V: X* W --------------------------------------------------------------------------
. z* y" n& B) Q8 m slack (VIOLATED) -0.86+ S. _+ b2 R+ _
, G2 F6 Q |/ |3 U4 m
, H: o9 R% A4 w! U/ X
請問該如何調整使他met呢?? |
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發表於 2007-12-24 09:53:47
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