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Startpoint: U_RST/nResetUSB_reg, }3 Y( Y# p) a
(falling edge-triggered flip-flop clocked by CLK48)
P/ B! D' I; Z1 W' M0 ] Endpoint: u_FUSB/FUS/BIF/PS/q_reg_2_
/ H3 ~# T- m0 L \ (rising edge-triggered flip-flop clocked by CLK48)2 C- p9 D! [- u# c
Path Group: CLK487 z8 D( |+ s) }8 R: r
Path Type: max6 ]& K% O2 D' H S' z+ M! ]# i7 ^
3 \. j1 o% D. p3 @ Point Incr Path
1 I0 X( b7 C) H& _" E --------------------------------------------------------------------------; x3 @8 c+ e4 H. k( G& Y! s: S/ x
clock CLK48 (fall edge) 9.00 9.00
6 ]1 n6 @' T2 s& y clock network delay (ideal) 2.00 11.009 n' g, I4 d$ ^, ^: h
U_RST/nResetUSB_reg/CKB (DBFRBN) 0.00 11.00 f! i+ z" e2 P, I+ n0 R, G
U_RST/nResetUSB_reg/Q (DBFRBN) 1.27 12.27 r6 A+ {. n, Q5 l: n7 ^
U_RST/nResetUSB (ResetGen) 0.00 12.27 r* M1 Y' }- Z: Z% G. { [
u_FUSB/RESETN (kFUS100_2m) 0.00 12.27 r" f p7 ]- U3 q# U# I
u_FUSB/U132/O (BUF1) 0.32 12.59 r
7 @6 ^4 M L# i1 w7 i4 `5 M: Z k2 w5 b u_FUSB/FUS/RESET_INN (LFUS) 0.00 12.59 r
+ Y. T3 n! Q2 \ u_FUSB/FUS/BIF/RESET_INN (LUSBIF) 0.00 12.59 r8 P3 p# {0 g: e% b
u_FUSB/FUS/BIF/U42/O (BUF1) 0.33 12.92 r+ B/ J- [3 O2 k9 T
u_FUSB/FUS/BIF/U49/O (AN2) 0.44 13.36 r3 G# @( x2 y, I z
u_FUSB/FUS/BIF/U50/O (AN2) 0.64 14.00 r
, }! j3 ]1 F# O u_FUSB/FUS/BIF/RESETN (LUSBIF) 0.00 14.00 r( H& r) B. h+ u) h( i
u_FUSB/FUS/U44/O (BUF1) 0.69 14.69 r
0 U+ q! ?* D; x2 S! y( ~ u_FUSB/FUS/LDSCR/RESETN (LDSCR) 0.00 14.69 r
+ b8 W, |8 ^+ u$ h) \8 P2 L u_FUSB/FUS/LDSCR/U85/O (INV1) 0.22 14.91 f0 {$ w5 o+ K2 u/ K( G
u_FUSB/FUS/LDSCR/U222/O (NR2) 0.46 15.37 r$ M6 t% S) J0 K& o3 T) w, n
u_FUSB/FUS/LDSCR/U8/O (AO12) 0.46 15.83 r
9 K2 d0 ~/ d" W; _ u_FUSB/FUS/LDSCR/U10/O (AN3) 0.50 16.33 r; `/ o% {& L N% M/ k0 v
u_FUSB/FUS/LDSCR/U7/O (AO222) 0.51 16.84 r& H. m, F: X9 t# E
u_FUSB/FUS/LDSCR/U206/O (AN2) 0.36 17.21 r! ^/ T6 A" U! C' @
u_FUSB/FUS/LDSCR/epC/InterruptRD (LDSC_EPC) 0.00 17.21 r
/ Q3 @* @4 y) @7 A' C' B4 M' O u_FUSB/FUS/LDSCR/epC/U87/O (INV1) 0.12 17.33 f
. R1 Y* E. H$ d2 m% j; o u_FUSB/FUS/LDSCR/epC/U83/O (OR3B2) 0.34 17.66 f
$ w: N, z2 c$ }3 e( T u_FUSB/FUS/LDSCR/epC/U82/O (NR2) 0.38 18.04 r# T8 |8 j9 I! o+ A, U
u_FUSB/FUS/LDSCR/epC/U63/O (AO112) 0.50 18.54 r
1 o: ]/ y( x4 ?9 z8 P* X u_FUSB/FUS/LDSCR/epC/D_epC[2] (LDSC_EPC) 0.00 18.54 r8 q& Q0 ?( O8 y6 X- O; j" f5 K5 L
u_FUSB/FUS/LDSCR/U158/O (ND2) 0.12 18.66 f
8 e( O7 E: r: i0 y8 V+ m7 m( V) j3 G; ^ u_FUSB/FUS/LDSCR/U156/O (OR3B2) 0.19 18.84 r
) r$ n; c* A j5 o$ y0 e u_FUSB/FUS/LDSCR/DD[2] (LDSCR) 0.00 18.84 r, [5 R% n8 y- k% ~( X6 B8 P/ T3 t
u_FUSB/FUS/MIS/DD[2] (LMISC) 0.00 18.84 r
1 w+ c) I7 M8 f8 S5 a5 Y u_FUSB/FUS/MIS/U47/O (AO222) 0.36 19.21 r
q" j3 x* U9 E+ J a8 ~* r V! T s u_FUSB/FUS/MIS/U45/O (OR2) 0.26 19.47 r
8 ?- I6 y- P# Q" M* C$ Z+ q u_FUSB/FUS/MIS/Q[2] (LMISC) 0.00 19.47 r
$ r) h! o$ v& U H; Z# X u_FUSB/FUS/BIF/DOUT[2] (LUSBIF) 0.00 19.47 r$ V4 y0 I7 i4 c
u_FUSB/FUS/BIF/U29/O (AO222) 0.32 19.79 r( L5 v" A6 S! t4 I* q, m& N B) v
u_FUSB/FUS/BIF/PS/DIN[2] (LP2S) 0.00 19.79 r
/ R1 I( P Y1 Q* {: j u_FUSB/FUS/BIF/PS/U6/O (AO222) 0.33 20.11 r+ N8 W. b8 q( y8 i7 {
u_FUSB/FUS/BIF/PS/q_reg_2_/D (QDFFN) 0.00 20.11 r* _2 M9 s) y7 q4 R5 B
data arrival time 20.11
2 M% [8 ^, h( V7 s# u1 Y( a3 }4 \# _
/ }! d) q5 [8 k clock CLK48 (rise edge) 18.00 18.00, q% ]0 e1 x6 w1 O2 o
clock network delay (ideal) 2.00 20.00
, Z0 H1 W \: ^" c# a clock uncertainty -0.50 19.505 H+ c) `+ X/ I: k
u_FUSB/FUS/BIF/PS/q_reg_2_/CK (QDFFN) 0.00 19.50 r- @# }8 B& l* t" N, |' v
library setup time -0.25 19.25" @. R" M# m, V1 O
data required time 19.25
# v" s/ u W) [. }; Q --------------------------------------------------------------------------' P# k7 w& w4 e: ?/ f; B( I
data required time 19.25
" V# v8 h$ P" ^! l! M: n' U2 v data arrival time -20.11& o- y& J5 i" o' ^+ ?
--------------------------------------------------------------------------
/ }. P9 J, p+ m1 }5 v slack (VIOLATED) -0.86
! U6 j! K2 Z+ C# n" x7 N; p# ~1 D" i/ c
0 S, l4 m' S0 L, @5 ^& C請問該如何調整使他met呢?? |
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