時間
5 r1 u2 f3 c2 o% C6 ^ | 活動內容 & T0 j! I: K* h; ~ T9 Q% c, u3 I, h
| 主講人 & Y7 P* D% e% S+ w$ n) }4 [' P
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1:00-1:30
9 D* }- b2 L. ~0 t7 e G: ] | Registration# i) u# H. y" b2 @. @9 X4 X
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1:30-1:35 9 J% G0 ~% I' `) ]- E+ u5 _
| Introduction: Agenda, who's here,8 V+ R) i5 A' S9 T8 @. x6 Q" |5 M
what do we do?
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1:35-2:05
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Note: Why prototype?
0 R6 N4 L: n$ Z* C. `) Y: S& w4 B0 YASIC Verification Options
- J8 U. `- E3 f8 S: D# T1 c& o* [ | Ashok Kulkarni,Technical
+ ^! t8 \2 \0 ^- H$ [3 IMarketing, Synplicity
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2:05-2:50
3 P& g& C: }9 ]7 W4 t' r | V5 for ASIC Prototype; h0 L: W! D: r( b a
| Simon Ho, Corporate Solution marketing Manager, Xilinx' z* [+ _1 G& e6 p) ?
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2:50-3:10 4 c' Y$ ~5 m+ G0 A
| Break
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3:10-3:55
6 `7 ]4 V1 s# W% B% i/ x# u7 | | Creating a platform around you FPGA(s) # w. @* Z, D$ a8 X* ~2 I7 {, l
| Ashok Kulkarni,Technical, A3 _/ l) @/ \. K
Marketing, Synplicity
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3:55-4:25
/ i! ~% T3 t) [9 g6 _+ i | Faster FPGA Implementation
2 x3 S2 M4 }$ f" j | Simon Ho, Corporate Solution marketing Manager, Xilinx( Q# d0 e. h0 Q' {) w
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4:25-5:00
+ G1 E$ R6 ?, S: O | Making the ASIC design ready for FPGA - HAPS live flow demo( c5 L) t% ~9 U6 H4 x
| Freddy Lin, ASIC Verification Specialist, Synplicity Taiwan0 A+ p* z$ q! W/ s) K
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5:00-5:30
7 Z9 m' [! ]# Y0 L2 C( \ | Q&A, Lucky Draw and Wrap-up
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