Item
2 X3 x8 o# B5 `- D: _ | SH77722 (SH-NaviJ2) Specifications
4 s' l3 P- s$ [9 D. S |
Type name3 [1 C5 ]2 b0 @
| R8A77722DA01BGV
% p! f# b" k& w& [: {4 \! c | R8A77722DA02BGV1 M+ G2 K& W+ B0 ~
|
Power supply voltage; S9 K5 G% u2 T- x& y2 h9 u4 r
| 1.15 to 1.3 V (internal), * a6 H! u; O) _1 E5 V& S7 d9 l
3.3 V and 1.8 V (external)
/ y2 J, j6 @' v; W' K6 a/ d | 1.2 to 1.35 V (internal),
- q0 v% |! {/ a8 s+ u3.3 V and 1.8 V (external)
6 V. y0 s" d: }6 `$ { |
Maximum operating frequency
% |% n$ M0 o) _3 \& c/ T3 S1 c2 n | 336 MHz) Z5 @0 F" [+ {; `3 E2 B
| 400 MHz! t5 k" W- m+ q1 D# |' m1 @
|
Processing performance
( G- ~0 T0 X; w$ X4 D& t( k1 a4 Z. { | 600MIPS, 2.3GFLOPS$ D2 Q2 j' B0 P* e8 a) [/ |
| 720MIPS, 2.8GFLOPS
3 j$ D8 x2 [; f) Y/ n+ H, W# O |
CPU core3 {/ S- r( u$ _, D1 c
| SH-4A core
! L5 X3 S! R4 i9 v" s |
On-chip RAM
) }9 s0 F. q, a. L | ILRAM: 16 Kbytes
! @1 P7 X1 _" e1 c( ] |
Cache memory4 c4 U6 Z; @. R2 @) Y7 Y
| 4-way set associative type with separate 32 Kbytes for instructions and 32 Kbytes for data
" V# l. ]/ g% c7 f8 j |
External memory: ?: V# L: D/ |! C" `: D
| DDR2-SDRAM (data transfer rate: 336 MHz) directly connectable to dedicated DDR2 bus% p- |! k$ l$ q. T" ?% z3 A8 @9 {
| DDR2-SDRAM (data transfer rate: 266 MHz) directly connectable to dedicated DDR2 bus7 l& H C; U7 z) J# j# u. a& a0 e
|
SRAM or ROM directly connected to extension bus
0 t- ~# b( ]' f6 A0 r/ O5 d7 n+ n |
Extension bus1 |* l7 a1 \" g; I' {
| Address space: 64 Mbytes × 3
3 J: {( J4 y6 r8 ^1 N5 i |
Main on-chip peripheral functions8 r# j- I" \0 |2 j4 L& l
| Renesas Graphics processor(2D/3D)! g2 J2 W" y, A1 |$ w
|
Display control: outputs for two screens (digital RGB and LVDS)5 o2 o, h/ _1 [9 z
|
Video input interface
+ ]- K6 F' m X, \3 g |
SD card host interface × 2 channels
7 w C1 t! S) b" y% W6 j. e) p6 | |
USB 2.0 host/function interface
7 d( B! ^( O9 ^& S! k) S |
FM multiplex decoder5 ~8 T$ t* \9 z/ B
|
Controller area network (RCAN) interface × 2 channels
3 G5 P/ }& g1 @1 r4 \8 O |
MOST interface module
' @8 Q6 p6 s9 ^; }8 s |
Various audio interfaces × 4 channels# L5 f7 f/ N$ i' v' i) [7 r& j. _
|
Dedicated DMAC × 26 channels; J) l# O, y4 c$ T' x0 Q P
|
I2C bus interface × 2 channels
, O' Q+ t7 H, C4 J% u |
Serial communication interface (SCIF) × 8 channels. A" z2 d8 ]* K, x8 \
|
Remote control interface × 1 channel
$ Z! {# j& `9 r1 O, ] |
A/D converter (10-bit) × 4 channels. V g4 S: J1 d
|
Timer × 9 channels. p7 f& @ Z/ d) W
|
On-chip debugging function3 `0 ~' S1 H9 Q; d+ F
|
Interrupt controller (INTC)
* X+ U$ B; ]. T+ Q |
Clock pulse generator (CPG): built-in PLL frequency multiplier) y; ~, {) G2 ` w( ~# q) M
|
Power-down modes5 I9 E/ Z' s# c5 C3 f) Z" }. @
| Sleep mode' s; s' p3 t; ^" c6 u H" o4 N
|
Module standby mode5 s, m2 k' j7 K3 l
|
DDR-SDRAM power supply backup mode$ O1 \* F' D% N) C% v+ |2 r) ?
|
Package2 M5 B1 J/ S% l% i% [
| 449-pin BGA (21 mm × 21 mm)3 D3 c2 b8 U/ Z5 F
|