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AMD Geode LX 800@0.9W處理器
General Features
: t. f' ~/ `1 K2 T, x3 ?$ K( r■ Functional blocks include:1 @7 U2 x1 ~8 I3 X5 T5 e3 t& S& F
— CPU Core2 w3 T8 |8 X1 t* U7 g
— GeodeLink™ Control Processor- x/ R% A9 g, d- K& x
— GeodeLink Interface Units
3 o' u& O3 X" v' y— GeodeLink Memory Controller
' q, x( b7 l7 h5 {" x5 K/ ^— Graphics Processor: j; S% W0 D F% s. d. v9 \% L* ~2 P
— Display Controller
" ], z+ G7 \: l( B9 V— Video Processor
9 }5 P% g5 [6 v! Q: x: }4 M– TFT Controller/Video Output Port
0 x# V! n8 D& g1 w: D— Video Input Port
# J4 w0 s. |. r3 O$ d— GeodeLink PCI Bridge
! A8 ~. A' W* C9 @3 ]/ w* u/ i0 G— Security Block! B! k( C% v& D1 k' N
■ 0.13 micron process. \6 a! v7 @2 ?% y* \
■ Packaging:3 R9 m5 `: g2 }3 ^& Z# `% o0 p& e
— 481-Terminal BGU (Ball Grid Array Cavity Up) with
- m8 L- c# f/ F. b3 kinternal heatspreader; M' `+ J3 \( c7 d! j
■ Single packaging option supports all features
9 N0 r: D, W' R% L4 B, uCPU Processor Features
* y3 X. R8 V0 h' j■ x86/x87-compatible CPU core$ |3 T: f* Q9 |( R
■ Performance:
1 m l% n0 G' u8 N0 w" X/ Q— Processor frequency: up to 500 MHz o6 y5 |' n. g' L
— Dhrystone 2.1 MIPs: 150 to 4508 s* o, y* j4 v+ W' U
— Fully pipelined FPU- F w' `" x( d; O3 y" L8 ]% p8 W' p
■ Split I/D cache/TLB (Translation Look-aside Buffer):# o. G" n" y+ z8 S: n
— 64 KB I-cache/64 KB D-cache
; o9 K u6 k3 R& \' W" d- H: Q) `' h: w— 128 KB L2 cache configurable as I-cache, D-cache,# n5 Q2 K% I& j; o: Y) D4 _
or both5 Z) q0 n. s5 _7 @8 i' y( i, ]$ i
■ Efficient prefetch and branch prediction
3 L8 [) t, N. \6 a■ Integrated FPU that supports the MMX® and
/ X& g# @* m3 qAMD 3DNow!™ instruction sets
y" ~. J( y6 e. w# U _- H5 ]" L■ Fully pipelined single precision FPU hardware with
! C# c, p) h2 ^# ~, U# a% bmicrocode support for higher precisions
5 q+ Y3 V; \2 r! a' V0 ~' NGeodeLink™ Control Processor6 x C9 c( u+ R) f* h! H( a
■ JTAG interface:
5 ^8 m- ?2 K* Z$ X0 G5 X _— ATPG, Full Scan, BIST on all arrays
; I6 e8 x9 M5 _4 x* o! l— 1149.1 Boundary Scan compliant
, R$ n$ w0 d6 G& d% P■ ICE (in-circuit emulator) interface; v) b# o' `" J
■ Reset and clock control
6 [$ p$ K% w$ c+ f■ Designed for improved software debug methods and& K1 q+ T" w: s) b. j; q* G% E
performance analysis% o. \" w% I+ p! D! L) c: }
■ Power Management:
, A: H& Z W+ K* [1 v! r& l# \" S— Total Dissipated Power (TDP) 3.8W, 1.6W typical @, [$ ~" r1 J. t. p5 _
500 MHz max power# z' d+ k$ d2 \
— GeodeLink active hardware power management3 n3 ^3 Z- K* N! ^1 f6 X4 |
— Hardware support for standard ACPI software power
4 I ?4 n* y" Ymanagement. v1 r8 T, F, o! R1 U, z2 T
— I/O companion SUSP/SUSPA power controls
! m- X& l m( b3 g5 I$ Y— Lower power I/O
, p; z2 E A0 \0 T4 l) |— Wakeup on SMI/INTR% [. h! k( z+ ]7 W
■ Designed to work in conjunction with the$ N8 n9 \5 Y6 `# l4 p
AMD Geode™ CS5536 companion device. Z+ P. N. m' F0 B! T
GeodeLink™ Architecture% ]# M4 ~# R' a& B4 i
■ High bandwidth packetized uni-directional bus for. G" }/ ]1 B, H8 E. b
internal peripherals
" w4 S5 f) a1 ?/ ?: \■ Standardized protocol to allow variants of products to be
8 a) v/ n. P* P+ i" n$ @! hdeveloped by adding or removing modules
, b |' o# @% t8 P2 u& y/ g) O! `■ GeodeLink Control Processor (GLCP) for diagnostics* e. Q1 J' [, o$ e3 b$ h
and scan control& n3 x( [# r5 `. t/ a5 \$ @! q4 q
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect4 ?( q4 O6 Z* [
GeodeLink™ Memory Controller1 X* ?/ J3 ]. @7 D. s& m* a! H* T
■ Integrated memory controller for low latency to CPU and0 b7 ]7 U4 d, w5 s' l
on-chip peripherals' t8 R; b# u# D7 C
■ 64-bit wide DDR SDRAM bus operating frequency:% g% T, |4 r6 _: \
— 200 MHz, 400 MT/S2 Y7 e/ m9 U) L0 j" i& n
■ Supports unbuffered DDR DIMMS using up to 1 GB) s3 f2 N4 @2 Z" b! `% z5 ?
DRAM technology
) y, O: S* L. O% G( d) m f■ Supports up to 2 DIMMS (16 devices max)8 T" x+ ~' W. h8 ]3 `# ^
2D Graphics Processor6 F! z( o I) i G, z4 E
■ High performance 2D graphics controller
' @ t3 W8 u# t' q! y$ W■ Alpha BLT8 E/ E6 ?. g% N4 F2 _% B' R
■ Microsoft® Windows® GDI GUI acceleration:
4 N7 h/ s) ? }. l# O8 t. ^6 l/ s6 x— Hardware support for all Microsoft RDP codes
# J3 `. z" E# H/ R# {■ Command buffer interface for asynchronous BLTs
0 Q! q8 P/ V0 b' R# K■ Second pattern channel support
1 ~0 o( t" Z! r/ F# s& \0 n" ^■ Hardware screen rotation |
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