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實驗平台~" Q- t; o7 S1 i5 b
「Terasic」Altera DE0 多媒體開發平台,Cyclone III 3C16 FPGA
4 L/ }' {" ^. c: G$ Y0 N在建構的過程中(僅放入cpu跟memory ip)1 y2 I: _, F- l! J* P
no reset vector has been specified for this CPU
! E, |0 b( [0 c+ {: C% d7 v" tno exception vector has been specified for this CPU/ C0 `: Z! b) u5 _1 k
這兩個訊息,沒辦法完全消除,這兩個一定要消除嗎4 T" J+ E- u+ h6 g% b* K; ~
試過* w# h, l" J) Q
on chip memory" m/ z7 M; ~% u* @: k
sdram
, P) R+ e( d/ e) T! B用上面兩個去試過所有可能的組合(mem/mem,sd/sd,sd/mem,mem/sd)
5 a$ O, x/ c: Ino reset vector has been specified for this CPU) Y; G8 O2 T1 x) g3 y
no exception vector has been specified for this CPU
6 g+ g% C9 } B. |5 Z4 ]' A總是會有一個沒辦法去除(先選的訊息會被消除)
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有人有在玩10.1版嗎?請多多幫忙~~
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; D5 X8 F3 d- k" @: l8 a目前打算~改用10.0sp1跟9.1sp2試試看2 @8 b6 D) r1 C0 i4 o
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THX~ |
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