Layout Guidelines for Optimized ESD Protection Diodes

semico_ljj

Layout Guidelines for Optimized ESD Protection Diodes

Karan Bhatia and Elyse Rosenbaum
! X5 C- w$ l7 h! v: ZDepartment of Electrical and Computer Engineering • University of Illinois at Urbana-Champaign
2 M% k$ U( F9 \1308 W. Main St., Urbana, IL 61801 • Tel. +1-217-244-0578 • Fax +1-217-244-1946 • Email: ksbhatia@uiuc.edu
/ a* w" d0 J: G* j3 q; R8 Q/ v2 ?
: u; U. O& R# {! H9 M2 f( ~Abstract - In this work, various layout options for ESD diodes’ PN junction geometry and metal routing are
* U7 d, o# C2 k! {  v, uinvestigated. The current compression point (ICP) is introduced to define the maximum current handling
capability of ESD protection devices. The figures-of-merit ICP/C and RON*C are used to compare the
performance of the structures investigated herein.

semico_ljj

The dual-diode circuit has been found to be a suitable
; D* V: M% `; B9 E! v4 FESD protection circuit for GHz-frequency CMOS
1 d$ r% Z+ x$ I- e3 q- a) U5 D+ l: OI/Os [1]. Layout-optimized ESD diodes provide a
6 D% R- ^& O" m9 y; Y+ Whigh protection level per unit capacitance (C),
minimizing the performance degradation they induce
1 V" {* P( J) H3 c% t2 }on high frequency I/O pins.

mousestack2003

感謝大大分享這些資料∼
. E% P! o8 K- w. y, k# p4 k
讓我們了解led的一些事情∼

majorchen

權限不夠,真想看看layout guide要注意什麼...
真是可惜...

guillermo

感謝樓主的分享!小弟最近剛好遇到ESD的問題!

dike

真想看看  與工做相關
5 u+ ?( g5 U+ b% `* |8 s4 m小弟最近剛好正在研究ESD中  謝謝

allenearl

发现一个很好的网站,有很多EMC&ESD设计方面的资料,完全免费的.
3 I% c- q  G: G7 [% t: i www.gooemc.cn

hing

很棒的參考資料，謝謝分享！

yoyoseven

謝謝你的分享
現在急需esd的防護方式