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回復 #1 option318 的帖子
回復 #1 option318 的帖子
4 }4 S3 c8 N( k$ Q' D; R) r* h(1) 首先 open loop gain(迴路頻寬K )must <= pfd之比較頻率之十分之一1 W0 J4 U( g- R, A3 h& |
否則(指>pfd之比較頻率之十分之一)要用Z domain 去分析charge pump- j% Z, ? g% \, H
pll ,且亦有unstability issue8 @8 o, e$ k& \9 q, @
(see Charge-pump phase lock loops paper by Gardner
2 m2 W; f, F$ X5 z: Y# x7 }& QIEEE Trans.Comm,vol Com-28,pp1849-1858,November 1980)
/ k9 T; o; M0 y; |' D- Q; L(2) loop BW is related to jitter (or phase noise) ,and locking time6 ?5 {8 r/ @1 D3 K$ P' O
so you have to consider loop BW from jitter & locking time spec X; |9 j# z* \" x8 r
(3)phase margin is decided by relation ship among zero freq ,loop unity gain freq , pole freq, N* ]) K: ]9 _' |1 G
(4) In my opinion ,gain margin is not considered in pll design |
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