在鎖相迴路中如何決定迴路頻寬K呢？

option318

　如題，請問先進們，在鎖相迴路中要如何決定迴路頻寬K呢？它又和Phase margin、Gain margin有關嗎？ :f17

kmchen3089

回復 #1 option318 的帖子
' E1 ?- n& ?, a% e9 r(1) 首先 open loop gain(迴路頻寬K )must <= pfd之比較頻率之十分之一
否則(指>pfd之比較頻率之十分之一)要用Z domain 去分析charge pump
pll ,且亦有unstability issue
2 M: D3 s- q  ^6 N8 g- q8 o(see Charge-pump phase lock loops paper by Gardner
IEEE Trans.Comm,vol Com-28,pp1849-1858,November 1980)
8 C; _3 D! B4 g. `(2) loop BW is related to jitter (or phase noise) ,and locking time
" q9 h0 [4 ^/ i. qso you have to consider loop BW  from jitter & locking time  spec
(3)phase margin is decided by relation ship among zero freq ,loop unity gain freq , pole freq
* J2 F# H& q- U9 I0 n1 d7 }# \) m(4) In my opinion ,gain margin is not considered in pll design

jasonxilion

gain margin is not considered in pll design？
3 h7 Q6 q% s% Q, Si don't think so.
isn't it dealt with the stability?

賴永諭

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