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Software Support , s, k" t- L3 _' E. b# }
- All MIG designs have been tested with ISE 9.1.01i and Synplicity 8.6.03i.
) Q$ ?6 B6 p8 R5 a. v
/ c) X1 G) g" N) ]Platform Support ]# B2 L0 E0 G! `6 ^8 {0 V* @
- Microsoft Windows XP (32 bit)
0 K+ w1 ]- [' T$ ?- }* ~7 O/ V1 _
Device Support # ^5 _0 `, B# k9 v( s4 [' X$ s
- All currently available Virtex-5, Virtex-4, Spartan-3, Spartan-3A, and Spartan-3E FPGAs are supported.
! A/ H9 i* f5 d( }" Z
( x: ]: M: a& N4 W. g, dNew Features 6 w, t) b& H1 r% Q% v
General New Features and Changes 7 J1 W& O. L* @" q/ q( |8 X5 R% t
- Supports "Create New Memory Part" for all the designs. 6 ~& V& P6 i7 r$ M
- DDR and DDR2 SDRAM designs for Spartan-3A. 8 x' p' i$ o& a, F
- DDR SDRAM is supported for Virtex-5. 1 |" ~0 j" \( x& y5 ]& B# {& g
- VHDL is supported for Virtex-5 DDR2 SDRAM and QDR II SRAM. ) o/ g" V- X9 Z( A* s/ l1 v/ s0 k
- MIG now pops up the design notes specific to the generated design. / F* _% O$ N5 p* m9 O
- Supports Pin Out compatibility with MIG 1.5 and MIG 1.6 for Spartan-3 and Spartan-3E designs. 1 X, m$ U9 t0 }: k/ i$ W1 b
- ECC check box changed to Combo box to support Pipelined and Un-pipelined modes. ! d! E* O9 h- J; r! c
- Support differential and nondifferential strobes for Spartan-3A DDR2 and Virtex-4 DDR2.
2 ^ d; h7 K! B4 k+ n! R1 ?- Pops up an information note if user selects the invalid data width or unsupported data width for a particular FPGA of Spartan-3/-3E/-3A.
( H( \5 A$ W( n5 M% r- Generates a script file for running MIG designs through Project Navigator GUI. This is supported only when the flow vendor is "XST".
& Q& x1 v) ^3 j. t- Default setting "DCI for Address and Control " is changed to "unChecked".
$ W9 p9 ~7 e2 m8 G- Frequency slider is changed to editable box in the GUI.
3 h- X. h! L5 V6 r- n4 c3 A) b- r- Supports only alphanumeric characters and underscore ('_') for the module name and also for the New Name in Edit Signal Names. $ ^2 u/ ^' ]* f" a8 z" g) n
- Removed console window when running MIG through CORE Generator.
5 n. B9 M' _, ?) ?6 t- WASSO table (Set Advanced Options) accepts only numeric characters.
1 y, b3 `; V) r- The maximum frequency for Spartan-3, -5 is set to 133 MHz if the data width is greater than 32. ( ^1 M6 Q; Q( o6 k' a% J$ F
- Provided web links for all XAPPs in the docs folder of the designs.
7 R H* V, T# I$ I- Provided link to Data Sheet instead of Log Sheet in the output window.
( V4 p$ ]. v7 M7 E- t- Support of Constraint "CONFIG PROHIBIT" while reading the ucf in the reserve pins window. ' B. _1 g' [/ p5 d
- WASSO limits the number of pins to be used in a bank per controller. For example in multi controller design, if WASSO is set to 10 in a bank, tool allocates 10 pins for each controller in that bank. 9 U4 {$ o! Z9 }9 O1 p5 T
- The designs are independent of the memory part package; hence, the package part of the memory component name is replaced with XX or XXX, where XX or XXX indicates don't care condition.
; B! ^. l1 D" c5 X
: y8 F, c7 Y& CVirtex-5 New Features and Changes 5 R( J% G x% Z* d# _: a
DDR2 SDRAM
6 w1 t' [7 u$ Y( Q# p" S7 Y- New controller with several high-performance features. All the features are described in detail in the Application Notes.
* J2 Q8 U/ t! z6 F' `' r$ Z$ T$ G- Enhanced data calibration algorithms for higher reliability.
) s& P( X7 k- ?1 ~# c! {% K7 _- Bank Management feature is supported.
9 v/ ^/ S# ?0 c& z O- Supports VHDL.
" u- N# L! F4 r {' W- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR2 bus. The controller now always forces this bit to 0 on the DDR2 bus, and the memory space presented to the user is now linear. 5 |3 I7 ]8 t1 s T, m# D2 F
- The User Interface bus has been modified. The command (read/write) is now presented on a separate bus from the address. See the MIG User's Guide for a definition of the User I/F bus.
; H+ |5 |+ \, \" k* ?* K% G: X1 U- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG1.7 and previous versions. - F; V: K# b# S
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 5 |% m. H, F* S
b. WASSO is applied to all the memory interface signals.
( R( M* _( ]# J- s4 ~c. Signals such as "Error" outputs are not part of the WASSO count. " S( g2 A. _; d9 |
& _! [8 j3 ~4 P# k/ BDDR SDRAM 3 U: ?$ a, ?, l! L% t4 n$ |
- This is a new design for MIG. Supports Verilog and VHDL.
3 b& K- o+ E! Q# W- Bank Management feature is supported.
& V0 _( |7 F* u7 d2 `7 T% a- The user is no longer required to always set address A10 (and skip this bit in their memory space) when issuing a command to the controller in order to prevent an auto-precharge from occurring on the DDR bus. The controller now always forces this bit to 0 on the DDR bus and the memory space presented to the user is now linear. & q) P' B* C1 w( v f- S
, Z8 ^# k7 Y* l; ^: BQDRII SRAM
- ], Z3 n. e {5 X$ a- Added support for VHDL. 3 b" u6 c4 L- |& ?( Q
- Added support for 72-bit designs. 8 Q) y& G( D" r$ C
- Added first level of calibration. This includes a dummy write of 1's and 0's to the memory. This pattern helps to calibrate for the CQ/Q delay. , d) A# ?) M6 n/ _1 ?/ r, I% t
- Moved the pattern generation to the phy_write module. This was in the test_data_gen in MIG 1.6 8 g( S" r! D6 k, y
- A user_qr_valid signal is now being generated to the backend. This signal helps generate the User_qen_n signal to the read data FIFOs. The MIG 1.6 code used the user_qr_empty from all the read data FIFOs. This change was done for timing reasons.
+ P; q9 d2 Y' N- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 4 Q- V2 g5 n L
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. & ^/ Q" e( K$ p$ m" Q4 \' n9 ^8 N
b. WASSO is applied to the output signals only. ! i5 e+ a: Q& k6 b* o3 M8 `
7 @3 M# e! u( S8 y# nVirtex-4 New Features and Changes O$ [1 p$ {3 X7 z. S& S% q
DDR2 SDRAM Direct Clocking $ u' e ~# y; @: v( e
- Calibration logic now centers and deskews each bit of data. This change improves the frequency performance of the design.
/ o; g& L% D, }# E- Z1 M9 m; i- Independent clock pins are generated for each load in deep designs. This change reduces the load on clock pins.
" j' |4 a" }1 x3 r- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. - y8 ?/ |/ g7 g2 ~$ @
- ECC check box changed to combo box to support Pipelined and Un-pipelined ECC options.
9 r* c6 i2 h: q u- E/ g8 O- DQS# Enable, burst type and ODT of 50 ohm are selectable from GUI through Mode registers.
6 b& l8 _0 ?2 r: J% s* R$ R- Removed all TIGs in UCF. The reset signal is now registered in every module. - [3 B. B1 p) A# E& o
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. : s8 L- a+ K# O: _" I4 h
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
/ z* N: |- ]" N3 [. ^! b- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
3 Y& C4 }+ N4 N. [( W- Replaced `defines with localparams for Verilog.
9 A1 }4 q8 W" N! I- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables.
+ |; o8 ]3 s* r; l7 T& j; Q- Several state machines now use "One-Hot Encoding". $ a# d' {$ L5 u; t! }2 T' h! D) \
- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. + Y- G/ E1 e: H% J) D
- Signal INIT_DONE is brought to top module. ; V9 `) m3 w$ _! }1 S7 I; {
- Removed the UniSim primitive components declaration from VHDL modules. - {, K& Q5 w0 z5 n7 U R
- We now support all multiples of 8-bit data widths even for x16 memory devices. / H. e% D% v2 f, u
- We support memory devices of speed grades -3 and -667.
F. Y' S7 o+ `6 z7 {# B- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. ' \+ H5 P# }( x- ~
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. . a' ^& l4 _0 N6 u
b. WASSO is applied to all the memory interface signals. # ~. K5 h9 c; u/ S1 r0 O
c. Signals such as "Error" outputs are not part of the WASSO count. ! K! P, f% k0 K6 I( h
2 l. U, n) I$ e* O7 Z7 w& ]DDR2 SDRAM SERDES Clocking
3 j1 r2 S: a% ~+ Y0 |& T) Q- Implemented a new calibration. This new algorithm reduces the DCM utilization and improves the timing analysis. More details are described in the application note.
- i& n, G- S; K) Z8 I, K- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. * `7 g4 v- h2 J, A6 P9 q- X
- Support for ODT. 2 {, N9 U0 X& k: V4 H" g
- DQS# Enable is selectable from GUI through Mode registers.
% [! p: N4 d. i: H+ n; T- Removed all TIGs in UCF. The reset signal is now registered in every module. / V) N; V& B! l# f6 f, Y6 C
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
5 f, J- D' Q) H9 N: N- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
3 S+ I/ s Y* a5 U- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
" R; |; c& C" P; ]' d" d8 I- Replaced `defines with localparams for Verilog.
) H9 _! i% M, v1 W6 l- Reset generation logic has been modified to make it synchronous with DCM Lock and DCM output clocks. ! D* l6 |: [! @8 x) u8 H) _; P
- Removed the UniSim primitive components declaration from VHDL modules. + K% ?8 a* K$ P. r+ n
- We now support all multiples of 8-bit data widths even for x16 memory devices.
* @: F/ r. g3 |+ l- Signal INIT_COMPLETE is brought to top module.
: ^3 ]0 w5 H& V# w3 ]- Memory devices of speed grades -5E and -40E are now supported.
& V: @$ i& F, ]- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions.
( H0 ?- }" ?, T6 M4 ka. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. ' l% I6 x1 ^3 v2 D' l9 Q
b. WASSO is applied to all the memory interface signals. ! h* h% L( j, k- O; ]. {9 e
c. Signals such as "Error" outputs are not part of the WASSO count.
9 j7 i7 W# g2 `- Y7 c* O3 B1 i
' l$ @1 ]# S7 F; |( f' |% qDDR SDRAM 3 N& u9 [9 r: N+ m
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
) H1 K9 ^$ \; l1 V9 M- Removed all TIGs in UCF. The reset signal is now registered in every module.
* T8 d, ?6 ^! V' k3 b, G- u. Y% M$ P- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. & E9 m5 r8 F4 h
- SYS_RESET_IN changed to SYS_RESET_IN_N, to follow standard convention for active low signal.
4 c0 x- @$ ?, i! P& v- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. ! `: l2 f8 q( h3 ]
- Replaced `defines with localparams for Verilog.
. ?* r* S) Y( y! I- t$ [- Read enable in the pattern calibration logic is now generated after comparing two positive edge data and two negative edge data. This removes any spurious read enables. 1 H" N c; U6 o8 P3 V0 u: ]
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
8 z% P- y- _, C- T- Removed the UniSim primitive components declaration from VHDL modules. ) U& k4 G5 Q4 B
- We now support all multiples of 8-bit data widths even for x16 memory devices.
; {/ X; ~* E: k+ F- The signal "init_done" is now a port in the top module. + H2 O) H K4 r; K( L
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. : U3 m" x! {2 b8 _4 j! `
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 0 e# J8 V7 Z5 A
b. WASSO is applied to all the memory interface signals. 6 M9 l; _" O1 k) b. I2 H
c. Signals such as "Error" outputs are not part of the WASSO count. 3 h, e1 V G% \
+ V9 u& n, \$ X5 G" r1 v1 X# X0 YRLDRAM II
# L7 T, N$ y% w" D( T; @9 l- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1. 2 Z, E6 r$ N8 X2 T2 N# M8 m
- Removed all TIGs in UCF. The reset signal is now registered in every module. ; L! G6 t5 U8 J5 F$ N3 d
- The design now uses CLK0, instead of CLK50 and div16clk. 9 _* z3 V6 Y, Z+ ]
- CLK200 is changed to differential clocks in mem_interface_top module (Design top).
6 g/ i" q1 m. x! b8 p1 ?- The signal sysReset is changed to sysReset_n, to follow standard convention for active low signal. 0 q+ a2 w$ |7 l
- Removed unused parameters from the parameter file.
/ \) U9 T/ R1 F" \# m- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity.
- Y6 D% t* ]6 z. A' e- Replaced `defines with localparams for Verilog. # X1 a4 r# J# v4 g
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
) t5 H `% h& U& i% Q/ z( n; l3 X- Removed the UniSim primitive components declaration from VHDL modules. * {( W+ W+ k1 H( Q" W& `$ ?" p( Y
- The signal "INIT_DONE" is now a port in the top module. & B) o/ s8 Q. d
- Test bench: The bank address sequence in backend_rom has been modified so that generation sequence starts with bank 0,1,.....,6,7. The command generation in the testbench is also pipelined for BL = 2,4,8.
O* I# S; l# I4 k" P" D- Replaced "tac" with "Q to data output" instead of "Q to any data output" in the timing spread sheets. " B; q& _1 K% d1 c' {
- The INITCNT that was hard coded in rld_rst module is parameterized according to frequency by adding a new parameter "INITCNT" in parameter file.
6 C: c* l4 S" R/ J- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. : Y9 h; [4 T' X9 e) `0 @
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 6 ~; {9 ^8 x( Y) V4 V+ {
b. WASSO count is applied on output signals only for SIO memory types.
) C0 L- ?- N8 b/ m1 {- P2 | Oc. QVLD, which is an input signal, is included in WASSO count for CIO memory types. This is the limitation of the current tool.
5 h3 F7 u% r( h3 `( d
( m+ E. Z1 ?) |QDRII SRAM / v4 q. b( Y! Z) L6 I
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
' p& M+ b3 L7 \9 A, X8 B7 y- Timing for the signal USER_QEN_n has been changed - it is one cycle late. A register for this signal has moved from the controller to the user logic. " i( n; ^0 w' x, R: V5 E K. {" X
- Supports generation of designs with out DCM. 0 p; }( I/ S$ D+ k. g0 S
- Part CY7C1526AV18-250BZC has been removed from Memory part list and added the CY7C1526V18-250BZC.
) X) z* p0 h5 }- Removed all TIGs in UCF. The reset signal is now registered in every module.
: q3 c2 c2 D0 ?3 k% E- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic. 5 X3 F3 i( M) H7 P8 a& J# I
- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. - Z) ^# o1 o" M. F
- Replaced `defines with localparams for Verilog. 7 d- x9 U" t& \9 f7 s
- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
5 b5 z4 j) @+ K. N [* k- Removed the UniSim primitive components declaration from VHDL modules. ' ^0 ~. w) v7 d8 I) c Y. l# g
- The signal "DLY_CAL_DONE" is now a port in the top module. ( @+ u$ A2 F6 q
- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable.
9 @+ M9 }! x1 l4 g. o3 c- Added support for DDR Byte writes. ' o/ A9 r/ h( p
- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 7 o3 r5 ^: m( B7 q& N/ V2 l
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals.
* v( y# k7 j* P3 Xb. WASSO is applied to the output signals only. - `' t O% _: x# S2 o# c) w+ U h3 d
c. K/K# clocks, which are outputs, are not included in WASSO count. This is a limitation of the current tool.
, R+ I% R# u- M" z" X1 B
1 {+ H' ?# q5 iDDRII SRAM * f+ w/ L. V) O9 h# g6 d
- There is a new option for the user to select the reset polarity. This option is in the parameter file. The parameter reset_active_low can be changed for active high reset. By default, this is set to 1.
, X! M& x, e% N E# }7 [- Timing for the signal USER_QEN_n has been changed -- it is one cycle late. A register for this signal has moved from the controller to the user logic.
* \$ v" A5 z w5 e( Z4 P! E. W" V- Supports generation of designs with out DCM. / w5 X. Z. i! w" f# {7 [6 j
- Part CY7C1526V18-250BZC has been removed from Memory Parts list.
5 S2 q; Q# ^7 r0 T! {$ Z- Removed all TIGs in UCF. The reset signal is now registered in every module. & V, _2 a( \; Z' e& k+ ?1 ]' k
- The IDELAY module now uses CLK0, instead of CLK50. CLK0 is used for the refresh counter. Previously, a divide clock was used for refresh logic.
" c6 a* v0 |" V' X$ d% u7 I- Removed XC_PROPS. The "defparams" that are defined for simulation will now work for both XST and Synplicity. + ^' v: {7 P$ K1 b; C" O
- Replaced `defines with localparams for Verilog.
2 }3 Y1 t0 p0 V0 M' x- Modified the reset generation logic to make it synchronous with DCM Lock and DCM output clocks.
; _$ I+ {" v8 R/ R- Removed the UniSim primitive components declaration from VHDL modules. 0 b. I* h9 ?. Z# O! z5 d
- The signal "DLY_CAL_DONE" is now a port in the top module. 0 {2 i/ c+ u7 Q" P# M+ D! t8 o
- The IO Standard generated for system signals are LVCMOS18. Users can change this as applicable.
3 ?, P2 e8 l; H% F- o: J- Added support for DDR Byte writes.
2 ~ _ [; C2 ^4 c) o3 z$ `- Several enhancements have been made to the pin allocation algorithms. Due to this, the pin outs will be different between MIG v1.7 and previous versions. 2 @; Y8 m' k& @% U- w. k
a. Increased efficiency when DCI is not used. MIG will now allocate VRP and VRN pins for other signals. 9 s9 J7 y! z0 m& D, S$ u
b. WASSO is applied to all the memory interface signals.
% T9 S3 Z) h' j0 t/ v# Yc. Signals such as "Error" outputs are included in WASSO count. |
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發表於 2007-7-24 12:23:39
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