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Design and Analysis of Technology Errors
d7 y% v: A6 m, Cfor CMOS Poly-silicon Capacitor
5 ~6 _/ u6 C5 p$ qZHUZhang-ming ,YANGYin-tang , ZHANGChun-peng , FUXiao-dong
; }9 m: ]7 F+ ^6 R" b9 w& K(Microelectronics Institute ,XidianUniversity,Xi’an 710071 , China)
3 c% l! j3 K% [( M0 @ D% `# Q0 ~Abstract : The technology errors of CMOS poly-silicon capacitor are analyzed .The effect of various errors introduced
4 R" g$ S4 e' T- y% y* W) {during fabrication on CMOS poly-silicon capacitor is discussed .Based on the improved design of unit-capacitors , the
& Z H5 P r+ S$ ^* n, C4 I* y* ecommon-centroid floorplan of poly-silicon capacitor is presented . On the proposed capacitor design way , the CMOS
. k0 ~' e. l/ c ~; c$ Eswitch-capacitor bandpass filters is implemented using 0.6μmCMOSDPDMprocess .Themeasured results of filters show
: I: X; z8 M* T8 y* w" _' b* gthat the proposed capacitor designway can be used to design high accuracy capacitors ,and applied to the design of submicro
H1 J5 |- k" r {3 R9 R, band deep sub-micro analog integrated circuit .( |. Y7 ~- S/ ?. B
' X: W) R5 m; ^0 Q' D7 k9 K回覆後 可以下載PDF附件 權限10 & 3RDB
: Z3 t# A o. |0 [$ \7 @9 R- \' F; U0 m& e1 H/ m s
3 `& q+ Y) D1 Z% i2 C" ?[ 本帖最後由 sjhor 於 2007-5-17 10:37 PM 編輯 ] |
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