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Design and Analysis of Technology Errors' f6 ]/ L* C0 m) u5 c+ X5 g: D
for CMOS Poly-silicon Capacitor
4 v- c/ _) S: Z3 cZHUZhang-ming ,YANGYin-tang , ZHANGChun-peng , FUXiao-dong
/ G$ F- s" r7 o& q4 l" Y(Microelectronics Institute ,XidianUniversity,Xi’an 710071 , China)
! V1 A4 j d( E- i! c3 ]Abstract : The technology errors of CMOS poly-silicon capacitor are analyzed .The effect of various errors introduced' A) `, v3 I' T& O8 j4 b1 r8 k
during fabrication on CMOS poly-silicon capacitor is discussed .Based on the improved design of unit-capacitors , the: b0 @7 y. D3 E) y# z
common-centroid floorplan of poly-silicon capacitor is presented . On the proposed capacitor design way , the CMOS$ Z: ?, j6 m V: D7 {" [! }; v- W
switch-capacitor bandpass filters is implemented using 0.6μmCMOSDPDMprocess .Themeasured results of filters show m+ U9 ?- Q7 h
that the proposed capacitor designway can be used to design high accuracy capacitors ,and applied to the design of submicro6 m& |+ [6 t; f0 b( X. j. E
and deep sub-micro analog integrated circuit .
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回覆後 可以下載PDF附件 權限10 & 3RDB
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[ 本帖最後由 sjhor 於 2007-5-17 10:37 PM 編輯 ] |
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